From e6c1be7e7fb2cb562672a006d893617654bb3ed7 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 13 Mar 2000 18:34:57 +0100 Subject: [PATCH] sparc.md: Remove all traces of TARGET_LIVE_G0. * config/sparc/sparc.md: Remove all traces of TARGET_LIVE_G0. (movsi_zero_liveg0): Remove. (movsf_insn_novis_liveg0): Remove. (negsi2): Remove. (negsi2_not_liveg0): Rename to negsi2. (one_cmplsi2): Remove. (one_cmplsi2_not_liveg0): Rename to one_cmplsi2. (one_cmplsi2_liveg0): Remove. * config/sparc/sparc.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE, MASK_LIVE_G0, MASK_BROKEN_SAVERESTORE): Remove. (CONDITIONAL_REGISTER_USAGE): Remove TARGET_LIVE_G0 if. (PREDICATE_CODES): Remove zero_operand. * config/sparc/sparc.c: Remove all traces of TARGET_LIVE_G0 and TARGET_BROKEN_SAVERESTORE. (zero_operand): Remove. * config/sparc/splet.h (SUBTARGET_SWITCHES): Remove -mlive-g0, -mno-live-g0, -mbroken-saverestore and -mno-broken-saverestore options. (SUBTARGET_OVERRIDE_OPTIONS): Remove. * config/sparc/linux-aout.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): Remove. * config/sparc/linux.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): Remove. * config/sparc/linux64.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): Remove. * config/sparc/sol2.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): Remove. * config/sparc/sparc.md (return_df_no_fpu): New pattern. From-SVN: r32508 --- gcc/ChangeLog | 32 +++++ gcc/config/sparc/linux-aout.h | 6 - gcc/config/sparc/linux.h | 6 - gcc/config/sparc/linux64.h | 6 - gcc/config/sparc/sol2.h | 6 - gcc/config/sparc/sparc.c | 57 +-------- gcc/config/sparc/sparc.h | 18 +-- gcc/config/sparc/sparc.md | 287 +++++++++++++----------------------------- gcc/config/sparc/splet.h | 25 +--- 9 files changed, 126 insertions(+), 317 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0d8d1d3..a6faefc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,35 @@ +2000-03-13 Jakub Jelinek + + * config/sparc/sparc.md: Remove all traces of TARGET_LIVE_G0. + (movsi_zero_liveg0): Remove. + (movsf_insn_novis_liveg0): Remove. + (negsi2): Remove. + (negsi2_not_liveg0): Rename to negsi2. + (one_cmplsi2): Remove. + (one_cmplsi2_not_liveg0): Rename to one_cmplsi2. + (one_cmplsi2_liveg0): Remove. + * config/sparc/sparc.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE, + MASK_LIVE_G0, MASK_BROKEN_SAVERESTORE): Remove. + (CONDITIONAL_REGISTER_USAGE): Remove TARGET_LIVE_G0 if. + (PREDICATE_CODES): Remove zero_operand. + * config/sparc/sparc.c: Remove all traces of TARGET_LIVE_G0 and + TARGET_BROKEN_SAVERESTORE. + (zero_operand): Remove. + * config/sparc/splet.h (SUBTARGET_SWITCHES): Remove -mlive-g0, + -mno-live-g0, -mbroken-saverestore and -mno-broken-saverestore + options. + (SUBTARGET_OVERRIDE_OPTIONS): Remove. + * config/sparc/linux-aout.h (TARGET_LIVE_G0, + TARGET_BROKEN_SAVERESTORE): Remove. + * config/sparc/linux.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): + Remove. + * config/sparc/linux64.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): + Remove. + * config/sparc/sol2.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE): + Remove. + + * config/sparc/sparc.md (return_df_no_fpu): New pattern. + 2000-03-13 Zack Weinberg * cpplib.c (do_pragma_implementation): Fix off-by-one error diff --git a/gcc/config/sparc/linux-aout.h b/gcc/config/sparc/linux-aout.h index 74ddd92..8063a6c 100644 --- a/gcc/config/sparc/linux-aout.h +++ b/gcc/config/sparc/linux-aout.h @@ -102,12 +102,6 @@ Boston, MA 02111-1307, USA. */ #define ASM_SPEC \ "%{V} %{v:%{!V:-V}} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}" -/* No weird SPARC variants on Linux */ -#undef TARGET_LIVE_G0 -#define TARGET_LIVE_G0 0 -#undef TARGET_BROKEN_SAVERESTORE -#define TARGET_BROKEN_SAVERESTORE 0 - /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special traps available which can get and set the condition codes reliably. */ diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index 630ca9c..75d0927 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -253,12 +253,6 @@ do { \ #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 #endif -/* No weird SPARC variants on Linux */ -#undef TARGET_LIVE_G0 -#define TARGET_LIVE_G0 0 -#undef TARGET_BROKEN_SAVERESTORE -#define TARGET_BROKEN_SAVERESTORE 0 - /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special traps available which can get and set the condition codes reliably. */ diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index 8d4672f..18a7f8b 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -378,12 +378,6 @@ do { \ /* #define DWARF_OFFSET_SIZE PTR_SIZE */ -/* No weird SPARC variants on Linux */ -#undef TARGET_LIVE_G0 -#define TARGET_LIVE_G0 0 -#undef TARGET_BROKEN_SAVERESTORE -#define TARGET_BROKEN_SAVERESTORE 0 - #if TARGET_ARCH32 /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special traps available which can get and set the condition codes diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 000fbc6..0304524 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -204,12 +204,6 @@ Boston, MA 02111-1307, USA. */ fixunsdfdi_libfunc \ = init_one_libfunc (TARGET_ARCH64 ? "__dtoul" : "__dtoull") -/* No weird SPARC variants on Solaris */ -#undef TARGET_LIVE_G0 -#define TARGET_LIVE_G0 0 -#undef TARGET_BROKEN_SAVERESTORE -#define TARGET_BROKEN_SAVERESTORE 0 - /* Solaris allows 64 bit out and global registers in 32 bit mode. sparc_override_options will disable V8+ if not generating V9 code. */ #undef TARGET_DEFAULT diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 0b9cd18..f7e0c22 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -377,8 +377,7 @@ v9_regcmp_p (code) /* Operand constraints. */ /* Return non-zero only if OP is a register of mode MODE, - or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because - %g0 may contain anything. */ + or const0_rtx. */ int reg_or_0_operand (op, mode) @@ -387,8 +386,6 @@ reg_or_0_operand (op, mode) { if (register_operand (op, mode)) return 1; - if (TARGET_LIVE_G0) - return 0; if (op == const0_rtx) return 1; if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE @@ -1132,16 +1129,6 @@ clobbered_register (op, mode) return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); } -/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */ - -int -zero_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return op == const0_rtx; -} - /* Return 1 if OP is a valid operand for the source of a move insn. */ int @@ -2369,12 +2356,6 @@ eligible_for_epilogue_delay (trial, slot) if (get_attr_length (trial) != 1) return 0; - /* If %g0 is live, there are lots of things we can't handle. - Rather than trying to find them all now, let's punt and only - optimize things as necessary. */ - if (TARGET_LIVE_G0) - return 0; - /* If there are any call-saved registers, we should scan TRIAL if it does not reference them. For now just make it easy. */ if (num_gfregs) @@ -2391,11 +2372,6 @@ eligible_for_epilogue_delay (trial, slot) return 0; } - /* If only trivial `restore' insns work, nothing can go in the - delay slot. */ - else if (TARGET_BROKEN_SAVERESTORE) - return 0; - pat = PATTERN (trial); /* Otherwise, only operations which can be done in tandem with @@ -3342,7 +3318,7 @@ output_function_prologue (file, size, leaf_function) if (actual_fsize == 0) /* do nothing. */ ; - else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE) + else if (! leaf_function) { if (actual_fsize <= 4096) fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); @@ -3357,26 +3333,6 @@ output_function_prologue (file, size, leaf_function) fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); } } - else if (! leaf_function && TARGET_BROKEN_SAVERESTORE) - { - /* We assume the environment will properly handle or otherwise avoid - trouble associated with an interrupt occurring after the `save' or - trap occurring during it. */ - fprintf (file, "\tsave\n"); - - if (actual_fsize <= 4096) - fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize); - else if (actual_fsize <= 8192) - { - fprintf (file, "\tadd\t%%fp, -4096, %%sp\n"); - fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096); - } - else - { - build_big_number (file, -actual_fsize, "%g1"); - fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n"); - } - } else /* leaf function */ { if (actual_fsize <= 4096) @@ -5632,8 +5588,7 @@ print_operand (file, x, code) { fputc ('[', file); /* Poor Sun assembler doesn't understand absolute addressing. */ - if (CONSTANT_P (XEXP (x, 0)) - && ! TARGET_LIVE_G0) + if (CONSTANT_P (XEXP (x, 0))) fputs ("%g0+", file); output_address (XEXP (x, 0)); fputc (']', file); @@ -6660,12 +6615,6 @@ sparc_flat_eligible_for_epilogue_delay (trial, slot) if (get_attr_length (trial) != 1) return 0; - /* If %g0 is live, there are lots of things we can't handle. - Rather than trying to find them all now, let's punt and only - optimize things as necessary. */ - if (TARGET_LIVE_G0) - return 0; - if (! reg_mentioned_p (stack_pointer_rtx, pat) && ! reg_mentioned_p (frame_pointer_rtx, pat)) return 1; diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index a099796..1f8b61f 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -522,20 +522,7 @@ extern int target_flags; #define MASK_STACK_BIAS 0x80000 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) -/* Non-zero means %g0 is a normal register. - We still clobber it as necessary, but we can't rely on it always having - a zero value. - We don't bother to support this in true 64 bit mode. */ -#define MASK_LIVE_G0 0x100000 -#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0) - -/* Non-zero means the cpu has broken `save' and `restore' insns, only - the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0). - We assume the environment will properly handle or otherwise avoid - trouble associated with an interrupt occurring after the `save' or trap - occurring during it. */ -#define MASK_BROKEN_SAVERESTORE 0x200000 -#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE) +/* 0x100000,0x200000 unused */ /* Non-zero means -m{,no-}fpu was passed on the command line. */ #define MASK_FPU_SET 0x400000 @@ -1042,8 +1029,6 @@ do \ fixed_regs[5] = 1; \ else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ fixed_regs[5] = 0; \ - if (TARGET_LIVE_G0) \ - fixed_regs[0] = 0; \ if (! TARGET_V9) \ { \ int regno; \ @@ -3370,7 +3355,6 @@ do { \ {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ {"clobbered_register", {REG}}, \ {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ -{"zero_operand", {CONST_INT}}, \ {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 8c781c1..efa572c 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -58,9 +58,6 @@ ;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding ;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of ;; 'f' for all DF/TFmode values, including those that are specific to the v8. -;; -;; -mlive-g0 is *not* supported for TARGET_ARCH64, so we don't bother to -;; test TARGET_LIVE_G0 if we have TARGET_ARCH64. ;; Attribute for cpu type. ;; These must match the values for enum processor_type in sparc.h. @@ -83,12 +80,6 @@ (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")] (const_string "arch32bit")))) -;; Whether -mlive-g0 is in effect. -(define_attr "live_g0" "no,yes" - (const - (cond [(symbol_ref "TARGET_LIVE_G0") (const_string "yes")] - (const_string "no")))) - ;; Insn type. Used to default other attribute values. ;; type "unary" insns have one input operand (1) and one output operand (0) @@ -749,7 +740,7 @@ (parallel [(set (match_operand:SI 0 "register_operand" "") (eq:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] - "! TARGET_LIVE_G0" + "" "{ operands[3] = gen_reg_rtx (SImode); }") (define_expand "seqdi_special" @@ -768,7 +759,7 @@ (parallel [(set (match_operand:SI 0 "register_operand" "") (ne:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] - "! TARGET_LIVE_G0" + "" "{ operands[3] = gen_reg_rtx (SImode); }") (define_expand "snedi_special" @@ -823,7 +814,7 @@ (define_expand "seq" [(set (match_operand:SI 0 "intreg_operand" "") (eq:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == SImode) @@ -876,7 +867,7 @@ (define_expand "sne" [(set (match_operand:SI 0 "intreg_operand" "") (ne:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == SImode) @@ -927,7 +918,7 @@ (define_expand "sgt" [(set (match_operand:SI 0 "intreg_operand" "") (gt:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) @@ -948,7 +939,7 @@ (define_expand "slt" [(set (match_operand:SI 0 "intreg_operand" "") (lt:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) @@ -969,7 +960,7 @@ (define_expand "sge" [(set (match_operand:SI 0 "intreg_operand" "") (ge:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) @@ -990,7 +981,7 @@ (define_expand "sle" [(set (match_operand:SI 0 "intreg_operand" "") (le:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) @@ -1011,7 +1002,7 @@ (define_expand "sgtu" [(set (match_operand:SI 0 "intreg_operand" "") (gtu:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (! TARGET_V9) @@ -1046,7 +1037,7 @@ (define_expand "sltu" [(set (match_operand:SI 0 "intreg_operand" "") (ltu:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (TARGET_V9) @@ -1060,7 +1051,7 @@ (define_expand "sgeu" [(set (match_operand:SI 0 "intreg_operand" "") (geu:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (TARGET_V9) @@ -1074,7 +1065,7 @@ (define_expand "sleu" [(set (match_operand:SI 0 "intreg_operand" "") (leu:SI (match_dup 1) (const_int 0)))] - "! TARGET_LIVE_G0" + "" " { if (! TARGET_V9) @@ -1118,7 +1109,7 @@ (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1138,7 +1129,7 @@ (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1245,7 +1236,7 @@ (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1265,7 +1256,7 @@ (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1377,7 +1368,7 @@ (const_int 0)) (match_operand:SI 2 "register_operand" "r"))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1387,7 +1378,7 @@ (const_int 0)) (match_operand:SI 2 "register_operand" ""))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) @@ -1400,7 +1391,7 @@ (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1410,7 +1401,7 @@ (ne:SI (match_operand:SI 1 "register_operand" "") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) @@ -1423,7 +1414,7 @@ (const_int 0)) (match_operand:SI 2 "register_operand" "r"))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1433,7 +1424,7 @@ (const_int 0)) (match_operand:SI 2 "register_operand" ""))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0)) @@ -1446,7 +1437,7 @@ (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" "#" [(set_attr "length" "2")]) @@ -1456,7 +1447,7 @@ (eq:SI (match_operand:SI 1 "register_operand" "") (const_int 0)))) (clobber (reg:CC 100))] - "! TARGET_LIVE_G0" + "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) @@ -1470,7 +1461,7 @@ (define_insn "*sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (ltu:SI (reg:CC 100) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "addx\\t%%g0, 0, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1478,7 +1469,7 @@ (define_insn "*neg_sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] - "! TARGET_LIVE_G0" + "" "subx\\t%%g0, 0, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1488,7 +1479,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0))) (match_operand:SI 1 "arith_operand" "rI")))] - "! TARGET_LIVE_G0" + "" "subx\\t%%g0, %1, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1497,7 +1488,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI"))))] - "! TARGET_LIVE_G0" + "" "subx\\t%%g0, %1, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1505,7 +1496,7 @@ (define_insn "*sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (geu:SI (reg:CC 100) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "subx\\t%%g0, -1, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1513,7 +1504,7 @@ (define_insn "*neg_sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] - "! TARGET_LIVE_G0" + "" "addx\\t%%g0, -1, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -1526,7 +1517,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI")))] - "! TARGET_LIVE_G0" + "" "addx\\t%%g0, %1, %0" [(set_attr "type" "misc") (set_attr "length" "1")]) @@ -2119,7 +2110,6 @@ /* Handle sets of MEM first. */ if (GET_CODE (operands[0]) == MEM) { - /* This checks TARGET_LIVE_G0 for us. */ if (reg_or_0_operand (operands[1], QImode)) goto movqi_is_ok; @@ -2180,7 +2170,6 @@ /* Handle sets of MEM first. */ if (GET_CODE (operands[0]) == MEM) { - /* This checks TARGET_LIVE_G0 for us. */ if (reg_or_0_operand (operands[1], HImode)) goto movhi_is_ok; @@ -2268,7 +2257,6 @@ /* Handle sets of MEM first. */ if (GET_CODE (operands[0]) == MEM) { - /* This checks TARGET_LIVE_G0 for us. */ if (reg_or_0_operand (operands[1], SImode)) goto movsi_is_ok; @@ -2327,15 +2315,6 @@ ; }") -;; Special LIVE_G0 pattern to obtain zero in a register. -(define_insn "*movsi_zero_liveg0" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "zero_operand" "J"))] - "TARGET_LIVE_G0" - "and\\t%0, 0, %0" - [(set_attr "type" "binary") - (set_attr "length" "1")]) - ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. (define_insn "*movsi_const64_special" @@ -2974,56 +2953,10 @@ ;; Floating point move insns -(define_insn "*movsf_insn_novis_liveg0" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m") - (match_operand:SF 1 "input_operand" "f,G,Q,*rR,S,m,m,f,*r"))] - "(TARGET_FPU && ! TARGET_VIS && TARGET_LIVE_G0) - && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" - "* -{ - if (GET_CODE (operands[1]) == CONST_DOUBLE - && (which_alternative == 2 - || which_alternative == 3 - || which_alternative == 4)) - { - REAL_VALUE_TYPE r; - long i; - - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); - REAL_VALUE_TO_TARGET_SINGLE (r, i); - operands[1] = GEN_INT (i); - } - - switch (which_alternative) - { - case 0: - return \"fmovs\\t%1, %0\"; - case 1: - return \"and\\t%0, 0, %0\"; - case 2: - return \"sethi\\t%%hi(%a1), %0\"; - case 3: - return \"mov\\t%1, %0\"; - case 4: - return \"#\"; - case 5: - case 6: - return \"ld\\t%1, %0\"; - case 7: - case 8: - return \"st\\t%1, %0\"; - default: - abort(); - } -}" - [(set_attr "type" "fpmove,move,move,move,*,load,fpload,fpstore,store") - (set_attr "length" "1")]) - -(define_insn "*movsf_insn_novis_noliveg0" +(define_insn "*movsf_insn_novis" [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m") (match_operand:SF 1 "input_operand" "f,G,Q,*rR,S,m,m,f,*rG"))] - "(TARGET_FPU && ! TARGET_VIS && ! TARGET_LIVE_G0) + "(TARGET_FPU && ! TARGET_VIS) && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" @@ -3204,7 +3137,7 @@ if (GET_CODE (operands[0]) == MEM) { if (register_operand (operands[1], SFmode) - || (! TARGET_LIVE_G0 && fp_zero_operand (operands[1], SFmode))) + || fp_zero_operand (operands[1], SFmode)) goto movsf_is_ok; if (! reload_in_progress) @@ -3246,7 +3179,7 @@ (define_insn "*clear_dfp" [(set (match_operand:DF 0 "memory_operand" "=m") (match_operand:DF 1 "fp_zero_operand" ""))] - "! TARGET_LIVE_G0 && TARGET_V9" + "TARGET_V9" "stx\\t%%g0, %0" [(set_attr "type" "store") (set_attr "length" "1")]) @@ -3623,7 +3556,7 @@ (define_insn "*clear_tfp" [(set (match_operand:TF 0 "memory_operand" "=m") (match_operand:TF 1 "fp_zero_operand" ""))] - "! TARGET_LIVE_G0 && TARGET_V9" + "TARGET_V9" "#" [(set_attr "type" "fpmove") (set_attr "length" "2")]) @@ -3631,7 +3564,7 @@ (define_split [(set (match_operand:TF 0 "memory_operand" "=m") (match_operand:TF 1 "fp_zero_operand" ""))] - "! TARGET_LIVE_G0 && TARGET_V9 && reload_completed" + "TARGET_V9 && reload_completed" [(set (subreg:DF (match_dup 0) 0) (match_dup 1)) (set (subreg:DF (match_dup 0) 8) (match_dup 1))] " @@ -4607,7 +4540,7 @@ [(set (reg:CC 100) (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r")) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "andcc\\t%0, 0xff, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -4616,7 +4549,7 @@ [(set (reg:CC 100) (compare:CC (match_operand:QI 0 "register_operand" "r") (const_int 0)))] - "! TARGET_LIVE_G0" + "" "andcc\\t%0, 0xff, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -4691,7 +4624,7 @@ [(set (reg:CC 100) (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "andcc\\t%0, 0xff, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -4916,11 +4849,10 @@ (match_operand:SI 1 "small_int_or_double" "n") (match_operand:SI 2 "small_int_or_double" "n")) (const_int 0)))] - "! TARGET_LIVE_G0 - && ((GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) > 19) - || (GET_CODE (operands[2]) == CONST_DOUBLE - && CONST_DOUBLE_LOW (operands[2]) > 19))" + "(GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 19) + || (GET_CODE (operands[2]) == CONST_DOUBLE + && CONST_DOUBLE_LOW (operands[2]) > 19)" "* { int len = (GET_CODE (operands[1]) == CONST_INT @@ -5686,7 +5618,7 @@ (compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r") (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "addcc\\t%0, %1, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -5885,7 +5817,7 @@ (compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ") (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "subcc\\t%r0, %1, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -6175,7 +6107,7 @@ (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] - "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0" + "TARGET_HARD_MUL32" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" [(set_attr "length" "2")]) @@ -6186,7 +6118,7 @@ (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "register_operand" "r")) (const_int 32))))] - "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0" + "TARGET_HARD_MUL32" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" [(set_attr "length" "2")]) @@ -6349,7 +6281,7 @@ (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] - "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0" + "TARGET_HARD_MUL32" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" [(set_attr "length" "2")]) @@ -6360,7 +6292,7 @@ (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "uns_small_int" "")) (const_int 32))))] - "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0" + "TARGET_HARD_MUL32" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" [(set_attr "length" "2")]) @@ -6450,7 +6382,7 @@ [(set (match_operand:SI 0 "register_operand" "") (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "") (match_operand:SI 2 "input_operand" "")))] - "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && ! TARGET_LIVE_G0" + "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" "") (define_insn "udivsi3_sp32" @@ -6459,7 +6391,7 @@ (match_operand:SI 2 "input_operand" "rI,m,r")))] "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) - && TARGET_ARCH32 && ! TARGET_LIVE_G0" + && TARGET_ARCH32" "* { output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands); @@ -6497,9 +6429,8 @@ (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") (udiv:SI (match_dup 1) (match_dup 2)))] - "(TARGET_V8 - || TARGET_DEPRECATED_V8_INSNS) - && ! TARGET_LIVE_G0" + "TARGET_V8 + || TARGET_DEPRECATED_V8_INSNS" "* { if (TARGET_V9) @@ -6953,7 +6884,7 @@ [(match_operand:SI 0 "arith_operand" "%r") (match_operand:SI 1 "arith_operand" "rI")]) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "%A2cc\\t%0, %1, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7004,7 +6935,7 @@ (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ") (match_operand:SI 1 "arith_operand" "rI"))) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "xnorcc\\t%r0, %1, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7053,7 +6984,7 @@ [(not:SI (match_operand:SI 0 "arith_operand" "rI")) (match_operand:SI 1 "reg_or_0_operand" "rJ")]) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "%B2cc\\t%r1, %0, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7125,8 +7056,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (reg:CC 100))] - "! TARGET_ARCH64 - && ! TARGET_LIVE_G0" + "TARGET_ARCH32" "#" [(set_attr "type" "unary") (set_attr "length" "2")]) @@ -7135,8 +7065,7 @@ [(set (match_operand:DI 0 "register_operand" "") (neg:DI (match_operand:DI 1 "register_operand" ""))) (clobber (reg:CC 100))] - "! TARGET_ARCH64 - && ! TARGET_LIVE_G0 + "TARGET_ARCH32 && reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5)) @@ -7157,28 +7086,10 @@ [(set_attr "type" "unary") (set_attr "length" "1")]) -(define_expand "negsi2" - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (match_operand:SI 1 "arith_operand" "")))] - "" - " -{ - if (TARGET_LIVE_G0) - { - rtx zero_reg = gen_reg_rtx (SImode); - - emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx)); - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_MINUS (SImode, zero_reg, - operands[1]))); - DONE; - } -}") - -(define_insn "*negsi2_not_liveg0" +(define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] - "! TARGET_LIVE_G0" + (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] + "" "sub\\t%%g0, %1, %0" [(set_attr "type" "unary") (set_attr "length" "1")]) @@ -7187,7 +7098,7 @@ [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "subcc\\t%%g0, %0, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7207,7 +7118,7 @@ (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] - "! TARGET_LIVE_G0" + "" "subcc\\t%%g0, %1, %0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7270,53 +7181,21 @@ [(set_attr "type" "unary,fp") (set_attr "length" "1")]) -(define_expand "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "") - (not:SI (match_operand:SI 1 "arith_operand" "")))] - "" - " -{ - if (TARGET_LIVE_G0 - && GET_CODE (operands[1]) == CONST_INT) - { - rtx zero_reg = gen_reg_rtx (SImode); - - emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx)); - emit_insn (gen_rtx_SET (VOIDmode, - operands[0], - gen_rtx_NOT (SImode, - gen_rtx_XOR (SImode, - zero_reg, - operands[1])))); - DONE; - } -}") - -(define_insn "*one_cmplsi2_not_liveg0" +(define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r,d") (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))] - "! TARGET_LIVE_G0" + "" "@ xnor\\t%%g0, %1, %0 fnot1s\\t%1, %0" [(set_attr "type" "unary,fp") (set_attr "length" "1,1")]) -(define_insn "*one_cmplsi2_liveg0" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (not:SI (match_operand:SI 1 "arith_operand" "r,d")))] - "TARGET_LIVE_G0" - "@ - xnor\\t%1, 0, %0 - fnot1s\\t%1, %0" - [(set_attr "type" "unary,fp") - (set_attr "length" "1,1")]) - (define_insn "*cmp_cc_not" [(set (reg:CC 100) (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "xnorcc\\t%%g0, %0, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -7336,7 +7215,7 @@ (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_dup 1)))] - "! TARGET_LIVE_G0" + "" "xnorcc\\t%%g0, %1, %0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -8054,7 +7933,7 @@ (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r") (const_int 1)) (const_int 0)))] - "! TARGET_LIVE_G0" + "" "addcc\\t%0, %0, %%g0" [(set_attr "type" "compare") (set_attr "length" "1")]) @@ -8955,8 +8834,6 @@ "TARGET_SPARCLITE || TARGET_SPARCLET" "* { - if (TARGET_LIVE_G0) - output_asm_insn (\"and %%g0,0,%%g0\", operands); return \"sub %%g0,%1,%0\;and %0,%1,%0\;scan %0,0,%0\;mov 32,%2\;sub %2,%0,%0\;sra %0,31,%2\;and %2,31,%2\;add %2,%0,%0\"; }" [(set_attr "type" "multi") @@ -9131,7 +9008,7 @@ [(set (match_operand:QI 0 "restore_operand" "") (match_operand:QI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "! TARGET_EPILOGUE" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9148,7 +9025,7 @@ [(set (match_operand:HI 0 "restore_operand" "") (match_operand:HI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "! TARGET_EPILOGUE" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9165,7 +9042,7 @@ [(set (match_operand:SI 0 "restore_operand" "") (match_operand:SI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "! TARGET_EPILOGUE" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9186,7 +9063,7 @@ [(set (match_operand:SF 0 "restore_operand" "=r") (match_operand:SF 1 "register_operand" "r")) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "! TARGET_EPILOGUE" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9198,12 +9075,26 @@ }" [(set_attr "type" "multi")]) +(define_insn "*return_df_no_fpu" + [(set (match_operand:DF 0 "restore_operand" "=r") + (match_operand:DF 1 "register_operand" "r")) + (return)] + "! TARGET_EPILOGUE && TARGET_ARCH64" + "* +{ + if (IN_OR_GLOBAL_P (operands[1])) + return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + else + return \"ret\;restore %%g0, %1, %Y0\"; +}" + [(set_attr "type" "multi")]) + (define_insn "*return_addsi" [(set (match_operand:SI 0 "restore_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI"))) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "! TARGET_EPILOGUE" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9223,7 +9114,7 @@ (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in"))) (return)] - "! TARGET_EPILOGUE && ! TARGET_LIVE_G0 && ! TARGET_CM_MEDMID" + "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID" "* { if (! TARGET_ARCH64 && current_function_returns_struct) diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h index d924e70..cd2f064 100644 --- a/gcc/config/sparc/splet.h +++ b/gcc/config/sparc/splet.h @@ -21,20 +21,13 @@ Boston, MA 02111-1307, USA. */ #include "sparc/aout.h" -/* -mbroken-saverestore is not included here because the long term - default is -mno-broken-saverestore. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE) -/* -mlive-g0 is only supported on the sparclet. */ #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ {"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \ -{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, \ -{"live-g0", MASK_LIVE_G0, "Use g0 as a normal register" }, \ -{"no-live-g0", -MASK_LIVE_G0, "Register g0 is fixed with a zero value" }, \ -{"broken-saverestore", MASK_BROKEN_SAVERESTORE, "Enable save/restore bug workarounds" }, \ -{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE, "Disable save/restore bug workarouns" }, +{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, #undef ASM_SPEC #define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)" @@ -51,19 +44,3 @@ Boston, MA 02111-1307, USA. */ #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) #undef WORDS_BIG_ENDIAN #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) - -#undef SUBTARGET_OVERRIDE_OPTIONS -#define SUBTARGET_OVERRIDE_OPTIONS \ - do { \ - if (TARGET_LIVE_G0) \ - { \ - warning ("Option '-mlive-g0' deprecated."); \ - target_flags &= ~MASK_LIVE_G0; \ - } \ - else if (TARGET_BROKEN_SAVERESTORE) \ - { \ - warning ("Option '-mbroken-saverestore' deprecated."); \ - target_flags &= ~MASK_BROKEN_SAVERESTORE; \ - } \ - } while (0) - -- 2.7.4