From e5fcce2d2b0a9ff048bc8f6aa0bb776a18a671c2 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Thu, 28 Apr 2016 19:49:18 +0000
Subject: [PATCH] [Hexagon] Add instruction aliases for vector unsigned
 compare-equal

Unsigned compare-equal instructions are mapped to signed compare-equal.

llvm-svn: 267925
---
 llvm/lib/Target/Hexagon/HexagonAlias.td | 65 +++++++++++++++++++++++++++++++++
 llvm/test/MC/Hexagon/v60-misc.s         | 36 ++++++++++++++++++
 2 files changed, 101 insertions(+)

diff --git a/llvm/lib/Target/Hexagon/HexagonAlias.td b/llvm/lib/Target/Hexagon/HexagonAlias.td
index e14e599..296c1765 100644
--- a/llvm/lib/Target/Hexagon/HexagonAlias.td
+++ b/llvm/lib/Target/Hexagon/HexagonAlias.td
@@ -27,3 +27,68 @@ def : InstAlias<"$Vd = #0",
 def : InstAlias<"$Vdd = #0",
       (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
       Requires<[HasV60T]>;
+
+// maps   "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
+def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
+      (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
+def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
+      (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
+def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
+      (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
+def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
+      (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
+def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
+      (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
+def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
+      (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
+def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
+      (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
+def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
+      (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
+def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
+      (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
+def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
+      (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
+def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
+      (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
+def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
+      (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
+      Requires<[HasV60T]>;
+
+// maps   "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
+def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
+      (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
+      Requires<[HasV60T]>;
diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s
index 335f029..b562010 100644
--- a/llvm/test/MC/Hexagon/v60-misc.s
+++ b/llvm/test/MC/Hexagon/v60-misc.s
@@ -8,3 +8,39 @@ v1:0 = #0
 
 # CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) }
 v1:0 = v3:2
+
+# CHECK: 1f90cf00 { q0 = vcmp.eq(v15.b,v16.b) }
+q0 = vcmp.eq(v15.ub, v16.ub)
+
+# CHECK: 1c92f101 { q1 &= vcmp.eq(v17.b,v18.b) }
+q1 &= vcmp.eq(v17.ub, v18.ub)
+
+# CHECK: 1c94f342 { q2 |= vcmp.eq(v19.b,v20.b) }
+q2 |= vcmp.eq(v19.ub, v20.ub)
+
+# CHECK: 1c96f583 { q3 ^= vcmp.eq(v21.b,v22.b) }
+q3 ^= vcmp.eq(v21.ub, v22.ub)
+
+# CHECK: 1f81c004 { q0 = vcmp.eq(v0.h,v1.h) }
+q0 = vcmp.eq(v0.uh, v1.uh)
+
+# CHECK: 1c83e205 { q1 &= vcmp.eq(v2.h,v3.h) }
+q1 &= vcmp.eq(v2.uh, v3.uh)
+
+# CHECK: 1c85e446 { q2 |= vcmp.eq(v4.h,v5.h) }
+q2 |= vcmp.eq(v4.uh, v5.uh)
+
+# CHECK: 1c87e687 { q3 ^= vcmp.eq(v6.h,v7.h) }
+q3 ^= vcmp.eq(v6.uh, v7.uh)
+
+# CHECK: 1f89c808 { q0 = vcmp.eq(v8.w,v9.w) }
+q0 = vcmp.eq(v8.uw, v9.uw)
+
+# CHECK: 1c8aea09 { q1 &= vcmp.eq(v10.w,v10.w) }
+q1 &= vcmp.eq(v10.uw, v10.uw)
+
+# CHECK: 1c8ceb46 { q2 |= vcmp.eq(v11.h,v12.h) }
+q2 |= vcmp.eq(v11.uw, v12.uw)
+
+# CHECK: 1c8eed8b { q3 ^= vcmp.eq(v13.w,v14.w) }
+q3 ^= vcmp.eq(v13.uw, v14.uw)
-- 
2.7.4