From e5784ef8f6c6a7779f5dfc8f989ea37d233be388 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 28 Aug 2020 16:21:34 -0700 Subject: [PATCH] [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. We weren't using this before, so none of the MachineFunction CFG edges had the branch probability information added. As a result, block placement later in the pipeline was flying blind. This is enabled only with optimizations enabled like SelectionDAG. Differential Revision: https://reviews.llvm.org/D86824 --- .../include/llvm/CodeGen/GlobalISel/IRTranslator.h | 6 +++-- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 18 ++++++++++---- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 2 +- llvm/lib/Target/Mips/MipsTargetMachine.cpp | 2 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 2 +- .../GlobalISel/irtranslator-condbr-lower-tree.ll | 14 +++++------ .../GlobalISel/irtranslator-switch-bittest.ll | 16 ++++++------- llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll | 2 -- .../AMDGPU/GlobalISel/divergent-control-flow.ll | 24 ++++++++++--------- llvm/test/CodeGen/X86/GlobalISel/phi.ll | 28 ++++++++++++---------- 13 files changed, 68 insertions(+), 52 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 8360e81..0674b53 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -27,6 +27,7 @@ #include "llvm/CodeGen/SwitchLoweringUtils.h" #include "llvm/IR/Intrinsics.h" #include "llvm/Support/Allocator.h" +#include "llvm/Support/CodeGen.h" #include #include @@ -556,6 +557,8 @@ private: /// Current target configuration. Controls how the pass handles errors. const TargetPassConfig *TPC; + CodeGenOpt::Level OptLevel; + /// Current optimization remark emitter. Used to report failures. std::unique_ptr ORE; @@ -659,8 +662,7 @@ private: BranchProbability Prob); public: - // Ctor, nothing fancy. - IRTranslator(); + IRTranslator(CodeGenOpt::Level OptLevel = CodeGenOpt::None); StringRef getPassName() const override { return "IRTranslator"; } diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 34ba473..8a39739 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -74,6 +74,7 @@ #include "llvm/Target/TargetMachine.h" #include #include +#include #include #include #include @@ -114,7 +115,8 @@ static void reportTranslationError(MachineFunction &MF, ORE.emit(R); } -IRTranslator::IRTranslator() : MachineFunctionPass(ID) { } +IRTranslator::IRTranslator(CodeGenOpt::Level optlevel) + : MachineFunctionPass(ID), OptLevel(optlevel) {} #ifndef NDEBUG namespace { @@ -158,6 +160,8 @@ void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addRequired(); + if (OptLevel != CodeGenOpt::None) + AU.addRequired(); getSelectionDAGFallbackAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU); } @@ -2912,14 +2916,20 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) { MRI = &MF->getRegInfo(); DL = &F.getParent()->getDataLayout(); ORE = std::make_unique(&F); + const TargetMachine &TM = MF->getTarget(); + EnableOpts = OptLevel != CodeGenOpt::None && !skipFunction(F); FuncInfo.MF = MF; - FuncInfo.BPI = nullptr; + if (EnableOpts) + FuncInfo.BPI = &getAnalysis().getBPI(); + else + FuncInfo.BPI = nullptr; + const auto &TLI = *MF->getSubtarget().getTargetLowering(); - const TargetMachine &TM = MF->getTarget(); + SL = std::make_unique(this, FuncInfo); SL->init(TLI, TM, *DL); - EnableOpts = TM.getOptLevel() != CodeGenOpt::None && !skipFunction(F); + assert(PendingPHIs.empty() && "stale PHIs"); diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index d7a14a3..6df717f 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -544,7 +544,7 @@ bool AArch64PassConfig::addInstSelector() { } bool AArch64PassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 5946249..f46349c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -946,7 +946,7 @@ bool GCNPassConfig::addInstSelector() { } bool GCNPassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 5068f9b..cf4115f 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -470,7 +470,7 @@ bool ARMPassConfig::addInstSelector() { } bool ARMPassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 5433b29..7e2c431 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -316,7 +316,7 @@ void MipsPassConfig::addPreEmitPass() { } bool MipsPassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index eeb0cab..1b305ea 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -147,7 +147,7 @@ bool RISCVPassConfig::addInstSelector() { } bool RISCVPassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 7616b2e..34bc72a 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -444,7 +444,7 @@ bool X86PassConfig::addInstSelector() { } bool X86PassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll index 173bc85..223fa28 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll @@ -5,7 +5,7 @@ declare i32 @bar(...) define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK-LABEL: name: or_cond ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK: successors: %bb.2(0x20000000), %bb.4(0x60000000) ; CHECK: liveins: $w0, $w1, $w2 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 @@ -19,7 +19,7 @@ define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BR %bb.4 ; CHECK: bb.4.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555) ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BR %bb.3 @@ -44,7 +44,7 @@ UnifiedReturnBlock: define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK-LABEL: name: and_cond ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.4(0x40000000), %bb.3(0x40000000) + ; CHECK: successors: %bb.4(0x60000000), %bb.3(0x20000000) ; CHECK: liveins: $w0, $w1, $w2 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 @@ -58,7 +58,7 @@ define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4 ; CHECK: G_BR %bb.3 ; CHECK: bb.4.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab) ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BR %bb.3 @@ -117,7 +117,7 @@ UnifiedReturnBlock: define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK-LABEL: name: or_cond_multiple_cases ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) + ; CHECK: successors: %bb.2(0x10000000), %bb.5(0x70000000) ; CHECK: liveins: $w0, $w1, $w2 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 @@ -132,12 +132,12 @@ define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind { ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BR %bb.5 ; CHECK: bb.5.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK: successors: %bb.2(0x12492492), %bb.4(0x6db6db6e) ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.2 ; CHECK: G_BR %bb.4 ; CHECK: bb.4.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555) ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: G_BRCOND [[ICMP5]](s1), %bb.2 ; CHECK: G_BR %bb.3 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll index 28756a4..8dfae82 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll @@ -4,7 +4,7 @@ define i32 @test_bittest(i16 %p) { ; CHECK-LABEL: name: test_bittest ; CHECK: bb.1 (%ir-block.0): - ; CHECK: successors: %bb.4(0x40000000), %bb.5(0x40000000) + ; CHECK: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) @@ -25,7 +25,7 @@ define i32 @test_bittest(i16 %p) { ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.3 ; CHECK: G_BR %bb.2 ; CHECK: bb.5 (%ir-block.0): - ; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000) + ; CHECK: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba) ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[ZEXT1]](s64) ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840 @@ -61,7 +61,7 @@ declare void @callee() define void @test_bittest_2_bt(i32 %p) { ; CHECK-LABEL: name: test_bittest_2_bt ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.5(0x40000000), %bb.6(0x40000000) + ; CHECK: successors: %bb.5(0x345d1746), %bb.6(0x4ba2e8ba) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176 @@ -71,7 +71,7 @@ define void @test_bittest_2_bt(i32 %p) { ; CHECK: G_BRCOND [[ICMP]](s1), %bb.5 ; CHECK: G_BR %bb.6 ; CHECK: bb.5.entry: - ; CHECK: successors: %bb.4(0x40000000), %bb.7(0x40000000) + ; CHECK: successors: %bb.4(0x0ccccccd), %bb.7(0x73333333) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C2]] ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](s32) @@ -80,7 +80,7 @@ define void @test_bittest_2_bt(i32 %p) { ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.4 ; CHECK: G_BR %bb.7 ; CHECK: bb.6.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) + ; CHECK: successors: %bb.2(0x76276276), %bb.5(0x09d89d8a) ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[SUB]](s32) ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 57351 @@ -90,7 +90,7 @@ define void @test_bittest_2_bt(i32 %p) { ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BR %bb.5 ; CHECK: bb.7.entry: - ; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000) + ; CHECK: successors: %bb.3(0x71c71c72), %bb.4(0x0e38e38e) ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64) ; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 365072220160 @@ -134,7 +134,7 @@ sw.default: ; preds = %entry define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) { ; CHECK-LABEL: name: test_bittest_single_bt_only_with_fallthrough ; CHECK: bb.1 (%ir-block.0): - ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK: successors: %bb.2(0x0aaaaaab), %bb.4(0x75555555) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) @@ -148,7 +148,7 @@ define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) { ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C3]] ; CHECK: G_BRCOND [[ICMP]](s1), %bb.2 ; CHECK: bb.4 (%ir-block.0): - ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: successors: %bb.3(0x745d1746), %bb.2(0x0ba2e8ba) ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C4]], [[ZEXT1]](s64) ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll index a4a1747..cbfadbd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll @@ -131,8 +131,6 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float ; CHECK: malloc ; CHECK: mov x21, x0 ; CHECK: strb w{{.*}}, [x0, #8] -; CHECK: fcmp -; CHECK: b.le ; CHECK: ret entry: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll index 4b8554b..bf1f0cc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll @@ -205,24 +205,26 @@ define amdgpu_kernel void @break_loop(i32 %arg) { ; CHECK-NEXT: ; implicit-def: $vgpr1 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0 -; CHECK-NEXT: BB5_1: ; %bb1 +; CHECK-NEXT: s_branch BB5_2 +; CHECK-NEXT: BB5_1: ; %Flow +; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3] +; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1] +; CHECK-NEXT: s_cbranch_execz BB5_4 +; CHECK-NEXT: BB5_2: ; %bb1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: v_add_u32_e32 v1, 1, v1 ; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1 -; CHECK-NEXT: s_cbranch_vccnz BB5_3 -; CHECK-NEXT: ; %bb.2: ; %bb4 -; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: s_cbranch_vccnz BB5_1 +; CHECK-NEXT: ; %bb.3: ; %bb4 +; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1 ; CHECK-NEXT: global_load_dword v2, v[0:1], off ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2 -; CHECK-NEXT: BB5_3: ; %Flow -; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1 -; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3] -; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] -; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1] -; CHECK-NEXT: s_cbranch_execnz BB5_1 -; CHECK-NEXT: ; %bb.4: ; %bb9 +; CHECK-NEXT: s_branch BB5_1 +; CHECK-NEXT: BB5_4: ; %bb9 ; CHECK-NEXT: s_endpgm bb: %id = call i32 @llvm.amdgcn.workitem.id.x() diff --git a/llvm/test/CodeGen/X86/GlobalISel/phi.ll b/llvm/test/CodeGen/X86/GlobalISel/phi.ll index 28e65c7..d2ce98d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/phi.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/phi.ll @@ -71,10 +71,11 @@ define i32 @test_i32(i32 %a, i32 %f, i32 %t) { ; ALL-NEXT: cmpl %ecx, %edi ; ALL-NEXT: setg %cl ; ALL-NEXT: testb $1, %cl -; ALL-NEXT: jne .LBB2_2 -; ALL-NEXT: # %bb.1: # %cond.false +; ALL-NEXT: je .LBB2_1 +; ALL-NEXT: # %bb.2: # %cond.end +; ALL-NEXT: retq +; ALL-NEXT: .LBB2_1: # %cond.false ; ALL-NEXT: movl %edx, %eax -; ALL-NEXT: .LBB2_2: # %cond.end ; ALL-NEXT: retq entry: %cmp = icmp sgt i32 %a, 0 @@ -99,10 +100,11 @@ define i64 @test_i64(i32 %a, i64 %f, i64 %t) { ; ALL-NEXT: cmpl %ecx, %edi ; ALL-NEXT: setg %cl ; ALL-NEXT: testb $1, %cl -; ALL-NEXT: jne .LBB3_2 -; ALL-NEXT: # %bb.1: # %cond.false +; ALL-NEXT: je .LBB3_1 +; ALL-NEXT: # %bb.2: # %cond.end +; ALL-NEXT: retq +; ALL-NEXT: .LBB3_1: # %cond.false ; ALL-NEXT: movq %rdx, %rax -; ALL-NEXT: .LBB3_2: # %cond.end ; ALL-NEXT: retq entry: %cmp = icmp sgt i32 %a, 0 @@ -126,10 +128,11 @@ define float @test_float(i32 %a, float %f, float %t) { ; ALL-NEXT: cmpl %eax, %edi ; ALL-NEXT: setg %al ; ALL-NEXT: testb $1, %al -; ALL-NEXT: jne .LBB4_2 -; ALL-NEXT: # %bb.1: # %cond.false +; ALL-NEXT: je .LBB4_1 +; ALL-NEXT: # %bb.2: # %cond.end +; ALL-NEXT: retq +; ALL-NEXT: .LBB4_1: # %cond.false ; ALL-NEXT: movaps %xmm1, %xmm0 -; ALL-NEXT: .LBB4_2: # %cond.end ; ALL-NEXT: retq entry: %cmp = icmp sgt i32 %a, 0 @@ -153,10 +156,11 @@ define double @test_double(i32 %a, double %f, double %t) { ; ALL-NEXT: cmpl %eax, %edi ; ALL-NEXT: setg %al ; ALL-NEXT: testb $1, %al -; ALL-NEXT: jne .LBB5_2 -; ALL-NEXT: # %bb.1: # %cond.false +; ALL-NEXT: je .LBB5_1 +; ALL-NEXT: # %bb.2: # %cond.end +; ALL-NEXT: retq +; ALL-NEXT: .LBB5_1: # %cond.false ; ALL-NEXT: movaps %xmm1, %xmm0 -; ALL-NEXT: .LBB5_2: # %cond.end ; ALL-NEXT: retq entry: %cmp = icmp sgt i32 %a, 0 -- 2.7.4