From e504a23b634dda6565e0bb58fb8ec6bd09c8d023 Mon Sep 17 00:00:00 2001 From: Zarko Todorovski Date: Thu, 25 Jun 2020 09:40:44 -0400 Subject: [PATCH] [NFC][PPC][AIX] Add stack frame layout diagram to PPCISelLowering.cpp Summary: This NFC patch adds a diagram of the AIX ABI stack frame layout. Based on https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/assembler/idalangref_runtime_process.html Reviewers: sfertile, cebowleratibm, hubert.reinterpretcast, Xiangling_L Reviewed By: sfertile Subscribers: wuzish, nemanjai, hiraditya, kbarton, llvm-commits Tags: #powerpc, #llvm Differential Revision: https://reviews.llvm.org/D82408 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 42 +++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 28bd806..c5b21b8 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7200,6 +7200,46 @@ static unsigned mapArgRegToOffsetAIX(unsigned Reg, const PPCFrameLowering *FL) { llvm_unreachable("Only general purpose registers expected."); } +// AIX ABI Stack Frame Layout: +// +// Low Memory +--------------------------------------------+ +// SP +---> | Back chain | ---+ +// | +--------------------------------------------+ | +// | | Saved Condition Register | | +// | +--------------------------------------------+ | +// | | Saved Linkage Register | | +// | +--------------------------------------------+ | Linkage Area +// | | Reserved for compilers | | +// | +--------------------------------------------+ | +// | | Reserved for binders | | +// | +--------------------------------------------+ | +// | | Saved TOC pointer | ---+ +// | +--------------------------------------------+ +// | | Parameter save area | +// | +--------------------------------------------+ +// | | Alloca space | +// | +--------------------------------------------+ +// | | Local variable space | +// | +--------------------------------------------+ +// | | Float/int conversion temporary | +// | +--------------------------------------------+ +// | | Save area for AltiVec registers | +// | +--------------------------------------------+ +// | | AltiVec alignment padding | +// | +--------------------------------------------+ +// | | Save area for VRSAVE register | +// | +--------------------------------------------+ +// | | Save area for General Purpose registers | +// | +--------------------------------------------+ +// | | Save area for Floating Point registers | +// | +--------------------------------------------+ +// +---- | Back chain | +// High Memory +--------------------------------------------+ +// +// Specifications: +// AIX 7.2 Assembler Language Reference +// Subroutine linkage convention + SDValue PPCTargetLowering::LowerFormalArguments_AIX( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Ins, const SDLoc &dl, @@ -7425,6 +7465,8 @@ SDValue PPCTargetLowering::LowerCall_AIX( const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, const CallBase *CB) const { + // See PPCTargetLowering::LowerFormalArguments_AIX() for a description of the + // AIX ABI stack frame layout. assert((CFlags.CallConv == CallingConv::C || CFlags.CallConv == CallingConv::Cold || -- 2.7.4