From e3f9361d493097a0bc70f131feafad0f89867d6e Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 26 Nov 2012 12:37:55 +0000 Subject: [PATCH] sourcebuild.texi: Document arm_v8_vfp_ok. gcc/ 2012-11-26 Kyrylo Tkachov * doc/sourcebuild.texi: Document arm_v8_vfp_ok. gcc/testsuite/ 2012-11-26 Kyrylo Tkachov * lib/target-supports.exp (check_effective_target_arm_v8_vfp_ok): New procedure. (add_options_for_arm_v8_vfp): New procedure. * gcc.target/arm/vrintaf32.c: New test. * gcc.target/arm/vrintaf64.c: Likewise. * gcc.target/arm/vrintmf32.c: Likewise. * gcc.target/arm/vrintmf64.c: Likewise. * gcc.target/arm/vrintpf32.c: Likewise. * gcc.target/arm/vrintpf64.c: Likewise. * gcc.target/arm/vrintrf32.c: Likewise. * gcc.target/arm/vrintrf64.c: Likewise. * gcc.target/arm/vrintxf32.c: Likewise. * gcc.target/arm/vrintxf64.c: Likewise. * gcc.target/arm/vrintzf32.c: Likewise. * gcc.target/arm/vrintzf64.c: Likewise. From-SVN: r193814 --- gcc/ChangeLog | 4 ++++ gcc/doc/sourcebuild.texi | 4 ++++ gcc/testsuite/ChangeLog | 18 ++++++++++++++++++ gcc/testsuite/gcc.target/arm/vrintaf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintaf64.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintmf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintmf64.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintpf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintpf64.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintrf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintrf64.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintxf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintxf64.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintzf32.c | 12 ++++++++++++ gcc/testsuite/gcc.target/arm/vrintzf64.c | 12 ++++++++++++ gcc/testsuite/lib/target-supports.exp | 23 +++++++++++++++++++++++ 16 files changed, 193 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/vrintaf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintaf64.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintmf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintmf64.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintpf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintpf64.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintrf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintrf64.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintxf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintxf64.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintzf32.c create mode 100644 gcc/testsuite/gcc.target/arm/vrintzf64.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 52b59c0..2a03bca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2012-11-26 Kyrylo Tkachov + * doc/sourcebuild.texi: Document arm_v8_vfp_ok. + +2012-11-26 Kyrylo Tkachov + * config/arm/arm.h (TARGET_FPU_ARMV8): New macro. * config/arm/arm.md (UNSPEC_VRINTZ, UNSPEC_VRINTP, UNSPEC_VRINTM) (UNSPEC_VRINTR, UNSPEC_VRINTX, UNSPEC_VRINTA): New unspecs. diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index ec8263f..0f29326 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1556,6 +1556,10 @@ ARM target generates Thumb-2 code for @code{-mthumb}. ARM target supports @code{-mfpu=vfp -mfloat-abi=softfp}. Some multilibs may be incompatible with these options. +@item arm_v8_vfp_ok +ARM target supports @code{-mfpu=fp-armv8 -mfloat-abi=softfp}. +Some multilibs may be incompatible with these options. + @item arm_prefer_ldrd_strd ARM target prefers @code{LDRD} and @code{STRD} instructions over @code{LDM} and @code{STM} instructions. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ce211d2..0dec0bf 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,21 @@ +2012-11-26 Kyrylo Tkachov + + * lib/target-supports.exp (check_effective_target_arm_v8_vfp_ok): + New procedure. + (add_options_for_arm_v8_vfp): New procedure. + * gcc.target/arm/vrintaf32.c: New test. + * gcc.target/arm/vrintaf64.c: Likewise. + * gcc.target/arm/vrintmf32.c: Likewise. + * gcc.target/arm/vrintmf64.c: Likewise. + * gcc.target/arm/vrintpf32.c: Likewise. + * gcc.target/arm/vrintpf64.c: Likewise. + * gcc.target/arm/vrintrf32.c: Likewise. + * gcc.target/arm/vrintrf64.c: Likewise. + * gcc.target/arm/vrintxf32.c: Likewise. + * gcc.target/arm/vrintxf64.c: Likewise. + * gcc.target/arm/vrintzf32.c: Likewise. + * gcc.target/arm/vrintzf64.c: Likewise. + 2012-11-26 Janus Weil PR fortran/54997 diff --git a/gcc/testsuite/gcc.target/arm/vrintaf32.c b/gcc/testsuite/gcc.target/arm/vrintaf32.c new file mode 100644 index 0000000..bea4aca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintaf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_roundf (x); +} + +/* { dg-final { scan-assembler-times "vrinta.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintaf64.c b/gcc/testsuite/gcc.target/arm/vrintaf64.c new file mode 100644 index 0000000..0c39347 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintaf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_round (x); +} + +/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintmf32.c b/gcc/testsuite/gcc.target/arm/vrintmf32.c new file mode 100644 index 0000000..33c2288 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintmf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_floorf (x); +} + +/* { dg-final { scan-assembler-times "vrintm.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintmf64.c b/gcc/testsuite/gcc.target/arm/vrintmf64.c new file mode 100644 index 0000000..d1b3db9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintmf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_floor (x); +} + +/* { dg-final { scan-assembler-times "vrintm.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintpf32.c b/gcc/testsuite/gcc.target/arm/vrintpf32.c new file mode 100644 index 0000000..ecea15d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintpf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_ceilf (x); +} + +/* { dg-final { scan-assembler-times "vrintp.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintpf64.c b/gcc/testsuite/gcc.target/arm/vrintpf64.c new file mode 100644 index 0000000..a4ce30d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintpf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_ceil (x); +} + +/* { dg-final { scan-assembler-times "vrintp.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintrf32.c b/gcc/testsuite/gcc.target/arm/vrintrf32.c new file mode 100644 index 0000000..f1b03be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintrf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_nearbyintf (x); +} + +/* { dg-final { scan-assembler-times "vrintr.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintrf64.c b/gcc/testsuite/gcc.target/arm/vrintrf64.c new file mode 100644 index 0000000..3f81718 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintrf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_nearbyint (x); +} + +/* { dg-final { scan-assembler-times "vrintr.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintxf32.c b/gcc/testsuite/gcc.target/arm/vrintxf32.c new file mode 100644 index 0000000..ca00b0f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintxf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_rintf (x); +} + +/* { dg-final { scan-assembler-times "vrintx.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintxf64.c b/gcc/testsuite/gcc.target/arm/vrintxf64.c new file mode 100644 index 0000000..9b86048 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintxf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_rint (x); +} + +/* { dg-final { scan-assembler-times "vrintx.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintzf32.c b/gcc/testsuite/gcc.target/arm/vrintzf32.c new file mode 100644 index 0000000..c76bf6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintzf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_truncf (x); +} + +/* { dg-final { scan-assembler-times "vrintz.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/vrintzf64.c b/gcc/testsuite/gcc.target/arm/vrintzf64.c new file mode 100644 index 0000000..602e876 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vrintzf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_trunc (x); +} + +/* { dg-final { scan-assembler-times "vrintz.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index af7fb94..5935346 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2091,6 +2091,22 @@ proc check_effective_target_arm_vfp_ok { } { } } +# Return 1 if this is an ARM target supporting -mfpu=fp-armv8 +# -mfloat-abi=softfp. +proc check_effective_target_arm_v8_vfp_ok {} { + if { [check_effective_target_arm32] } { + return [check_no_compiler_messages arm_v8_vfp_ok object { + int foo (void) + { + __asm__ volatile ("vrinta.f32.f32 s0, s0"); + return 0; + } + } "-mfpu=fp-armv8 -mfloat-abi=softfp"] + } else { + return 0 + } +} + # Return 1 if this is an ARM target supporting -mfpu=vfp # -mfloat-abi=hard. Some multilibs may be incompatible with these # options. @@ -2143,6 +2159,13 @@ proc add_options_for_arm_neon { flags } { return "$flags $et_arm_neon_flags" } +proc add_options_for_arm_v8_vfp { flags } { + if { ! [check_effective_target_arm_v8_vfp_ok] } { + return "$flags" + } + return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp" +} + # Add the options needed for NEON. We need either -mfloat-abi=softfp # or -mfloat-abi=hard, but if one is already specified by the # multilib, use it. Similarly, if a -mfpu option already enables -- 2.7.4