From e3f0455ba6bfed94442dd449f743c04ba72aa9d9 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Fri, 25 Jul 2014 19:34:21 +0900 Subject: [PATCH] drm/exynos: control blending of mixer graphic layer 0 The mixer graphic layer 0 isn't blended as default by commit 0377f4ed9f1aed30292c4e3c87f24e028ae26f36(drm/exynos: Don't blend mixer layer 0). But it needs to be blended with graphic layer 0 if video layer is enabled by vp because video layer is bottom. Change-Id: I3c4a18c569463fab5cd210e654428bfae8fd5e2d Signed-off-by: Joonyoung Shim --- drivers/gpu/drm/exynos/exynos_mixer.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 5c1ebba..5a46267 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -359,6 +359,11 @@ static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable) vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_VP_ENABLE); + + /* control blending of graphic layer 0 */ + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val, + MXR_GRP_CFG_BLEND_PRE_MUL | + MXR_GRP_CFG_PIXEL_BLEND_EN); } break; } -- 2.7.4