From e3a4c7c92a87eab0a9ba14aef0230975e6586eee Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Thu, 15 Jan 2015 14:22:17 +0900 Subject: [PATCH] arm64: dts: exynos: Add USB3.0 Host dt node for Exynos5433 This patch adds PHY and USB3.0 Host device tree node using DWC3 chip and set USB3.0 Host related clock parent for Exynos5433. Cc: Kukjin Kim Signed-off-by: Jaewon Kim Signed-off-by: Chanwoo Choi Acked-by: Inki Dae --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 46 ++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7676edb..fbaaa98 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1006,6 +1006,52 @@ samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; }; + + usbdrd_phy1: phy@15580000 { + compatible = "samsung,exynos5433-usbdrd-phy"; + reg = <0x15580000 0x100>; + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>; + assigned-clock-parents = + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbdrd3_1: usb@15a00000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; + assigned-clock-parents = + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <0>, <66700000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x154a0000 0x10000>; + interrupts = <0 244 0>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; timer { -- 2.7.4