From e3a464aeec60bdd01085dddb47a0c7a192e7fe71 Mon Sep 17 00:00:00 2001 From: ciceron Date: Tue, 2 Mar 2004 21:06:24 +0000 Subject: [PATCH] * config/m68hc11/m68hc11.md (SOFT_TMP_REGNUM): Define. (SOFT_XY_REGNUM): Define. (cmp split): Use the above instead of hard coded numbers. (8-bit op split): No need to check the mode; allow Q_REG. (ashift split): Adjust the first operand if it uses the SP and we are pushing the shifted value. (plus shift split): Fix when a source is in register D+X. ("doloop_end"): Pass dummy arguments to gen_rtx_NE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@78781 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/m68hc11/m68hc11.md | 35 +++++++++++++++++++++++++++-------- 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index af21040..f8a1e26 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2004-03-02 Stephane Carrez + * config/m68hc11/m68hc11.md (SOFT_TMP_REGNUM): Define. + (SOFT_XY_REGNUM): Define. + (cmp split): Use the above instead of hard coded numbers. + (8-bit op split): No need to check the mode; allow Q_REG. + (ashift split): Adjust the first operand if it uses the SP and we + are pushing the shifted value. + (plus shift split): Fix when a source is in register D+X. + ("doloop_end"): Pass dummy arguments to gen_rtx_NE. + +2004-03-02 Stephane Carrez + * config/m68hc11/m68hc11.c (m68hc11_check_z_replacement): Fix when comparing with Z register. diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md index deea231..335095e 100644 --- a/gcc/config/m68hc11/m68hc11.md +++ b/gcc/config/m68hc11/m68hc11.md @@ -144,7 +144,9 @@ (A_REGNUM 5) ; A (high part of D) (B_REGNUM 6) ; B (low part of D) (CC_REGNUM 7) ; Condition code register - (SOFT_Z_REGNUM 11) ; Z soft register + (SOFT_TMP_REGNUM 10) ; TMP soft register + (SOFT_Z_REGNUM 11) ; Z soft register + (SOFT_XY_REGNUM 12) ; XY soft register ]) ;;-------------------------------------------------------------------- @@ -252,7 +254,7 @@ [(set (cc0) (match_operand:QI 0 "tst_operand" "m")) (use (match_operand:HI 1 "hard_reg_operand" "dxy")) - (use (reg:HI 11))] + (use (reg:HI SOFT_Z_REGNUM))] "" "#") @@ -937,9 +939,9 @@ (define_split [(set (match_operand:QI 0 "hard_addr_reg_operand" "") (match_operand:QI 1 "general_operand" ""))] - "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode + "z_replacement_completed == 2 && !reg_mentioned_p (operands[0], operands[1]) - && !D_REG_P (operands[1])" + && !(D_REG_P (operands[1]) || Q_REG_P (operands[1]))" [(parallel [(set (reg:HI D_REGNUM) (match_dup 2)) (set (match_dup 2) (reg:HI D_REGNUM))]) (set (reg:QI D_REGNUM) (match_dup 1)) @@ -953,9 +955,9 @@ (define_split [(set (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "hard_addr_reg_operand" ""))] - "z_replacement_completed == 2 && GET_MODE (operands[1]) == QImode + "z_replacement_completed == 2 && !reg_mentioned_p (operands[1], operands[0]) - && !D_REG_P (operands[0])" + && !(D_REG_P (operands[0]) || Q_REG_P (operands[0]))" [(parallel [(set (reg:HI D_REGNUM) (match_dup 2)) (set (match_dup 2) (reg:HI D_REGNUM))]) (set (match_dup 0) (reg:QI D_REGNUM)) @@ -4443,6 +4445,13 @@ { m68hc11_split_move (m68hc11_gen_lowpart (SImode, operands[0]), const0_rtx, operands[2]); + + /* Adjust first operand if it uses SP so that we take into + account the above push. Can occur only for 68HC12. */ + if (reg_mentioned_p (gen_rtx (REG, HImode, HARD_SP_REGNUM), + operands[1])) + operands[1] = adjust_address (operands[1], + GET_MODE (operands[0]), 4); } m68hc11_split_move (m68hc11_gen_highpart (SImode, operands[0]), m68hc11_gen_lowpart (SImode, operands[1]), @@ -4531,14 +4540,24 @@ (const_int 16)) (match_operand:SI 2 "general_operand" "")))] "z_replacement_completed == 2 && X_REG_P (operands[1])" - [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM)) + [(set (reg:HI D_REGNUM) (match_dup 5)) (set (reg:HI X_REGNUM) (match_dup 3)) (set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 4))) (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM) (const_int 0)) (reg:HI CC_REGNUM)))] "operands[3] = m68hc11_gen_highpart (HImode, operands[2]); - operands[4] = m68hc11_gen_lowpart (HImode, operands[2]);") + if (X_REG_P (operands[2])) + { + operands[4] = gen_rtx (REG, HImode, HARD_X_REGNUM); + operands[5] = gen_rtx (REG, HImode, HARD_D_REGNUM); + } + else + { + operands[4] = m68hc11_gen_lowpart (HImode, operands[2]); + operands[5] = gen_rtx (REG, HImode, HARD_X_REGNUM); + } +") (define_insn "addsi_ashift16" [(set (match_operand:SI 0 "register_operand" "=D") -- 2.7.4