From e2ebe8b29207a41c43069d23d3019c93eb302b51 Mon Sep 17 00:00:00 2001
From: Jian Hu <jian.hu@amlogic.com>
Date: Sun, 30 Sep 2018 15:53:28 +0800
Subject: [PATCH] clock: fix coverity warning

PD#174376: clock: fix coverity warning

Fix suspicious implicit sign extension,
val << (shift), the val is defined as u16, after
shift to left,the val maybe overflow, a u32 variable
should instead of "val << (shift)".

Change-Id: I5b481c2b5d249426c20973fb261fb5ba905528f7
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
 drivers/amlogic/clk/axg/axg_clk-pll.c        | 16 +++++++++++-----
 drivers/amlogic/clk/clk-cpu-fclk-composite.c |  8 +++++---
 drivers/amlogic/clk/clk-pll.c                | 16 +++++++++++-----
 drivers/amlogic/clk/g12a/g12a_clk-pll.c      | 16 +++++++++++-----
 drivers/amlogic/clk/tl1/tl1_clk-pll.c        | 16 +++++++++++-----
 5 files changed, 49 insertions(+), 23 deletions(-)

diff --git a/drivers/amlogic/clk/axg/axg_clk-pll.c b/drivers/amlogic/clk/axg/axg_clk-pll.c
index 8e204f3..27cc75a 100644
--- a/drivers/amlogic/clk/axg/axg_clk-pll.c
+++ b/drivers/amlogic/clk/axg/axg_clk-pll.c
@@ -175,6 +175,7 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct parm *p;
 	const struct pll_rate_table *rate_set;
 	unsigned long old_rate;
+	unsigned int tmp;
 	int ret = 0;
 	u32 reg;
 	unsigned long flags = 0;
@@ -256,30 +257,35 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	reg = readl(pll->base + p->reg_off);
 
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
+	tmp = rate_set->n;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->m;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
+	tmp = rate_set->m;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
+	tmp = rate_set->od;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od2;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
+		tmp = rate_set->od2;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
 	p = &pll->frac;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
+		tmp = rate_set->frac;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
diff --git a/drivers/amlogic/clk/clk-cpu-fclk-composite.c b/drivers/amlogic/clk/clk-cpu-fclk-composite.c
index ba722e5..074e0c7 100644
--- a/drivers/amlogic/clk/clk-cpu-fclk-composite.c
+++ b/drivers/amlogic/clk/clk-cpu-fclk-composite.c
@@ -205,6 +205,7 @@ static int meson_fclk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 	u32  val, final_dyn_mask;
 	u8 final_dyn_shift;
 	unsigned long old_rate;
+	unsigned int tmp;
 	unsigned long flags = 0;
 
 	if (parent_rate == 0 || rate == 0)
@@ -235,11 +236,12 @@ static int meson_fclk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 		__acquire(mux_divider->lock);
 	writel((val | MESON_DYN_ENABLE), mux_divider->reg);
 	/*set mux_divider clk divider*/
-	val = PARM_SET(p_div->width, p_div->shift, val, rate_set->mux_div);
+	tmp = rate_set->mux_div;
+	val = PARM_SET(p_div->width, p_div->shift, val, tmp);
 	writel(val, mux_divider->reg);
 	/*set mux_divider postmux*/
-	val = PARM_SET(p_postmux->width, p_postmux->shift, val,
-			rate_set->postmux);
+	tmp = rate_set->postmux;
+	val = PARM_SET(p_postmux->width, p_postmux->shift, val, tmp);
 	writel(val, mux_divider->reg);
 	/*set mux_divider final dyn*/
 	val = readl(mux_divider->reg);
diff --git a/drivers/amlogic/clk/clk-pll.c b/drivers/amlogic/clk/clk-pll.c
index 55be73a..ced3ae4 100644
--- a/drivers/amlogic/clk/clk-pll.c
+++ b/drivers/amlogic/clk/clk-pll.c
@@ -163,6 +163,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct parm *p;
 	const struct pll_rate_table *rate_set;
 	unsigned long old_rate;
+	unsigned int tmp;
 	int ret = 0;
 	u32 reg;
 
@@ -224,30 +225,35 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	reg = readl(pll->base + p->reg_off);
 
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
+	tmp = rate_set->n;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->m;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
+	tmp = rate_set->m;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
+	tmp = rate_set->od;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od2;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
+		tmp = rate_set->od2;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
 	p = &pll->frac;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
+		tmp = rate_set->frac;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
index 40facab..858a088 100644
--- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c
+++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
@@ -225,6 +225,7 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct parm *p;
 	const struct pll_rate_table *rate_set;
 	unsigned long old_rate;
+	unsigned long tmp;
 	int ret = 0;
 	u32 reg;
 	unsigned long flags = 0;
@@ -390,12 +391,14 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	reg = readl(pll->base + p->reg_off);
 
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
+	tmp = rate_set->n;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->m;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
+	tmp = rate_set->m;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od;
@@ -407,20 +410,23 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		goto OUT;
 	}
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
+	tmp = rate_set->od;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od2;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
+		tmp = rate_set->od2;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
 	p = &pll->frac;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
+		tmp = rate_set->frac;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
diff --git a/drivers/amlogic/clk/tl1/tl1_clk-pll.c b/drivers/amlogic/clk/tl1/tl1_clk-pll.c
index 8a9f42f..6a8a81f 100644
--- a/drivers/amlogic/clk/tl1/tl1_clk-pll.c
+++ b/drivers/amlogic/clk/tl1/tl1_clk-pll.c
@@ -192,6 +192,7 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct parm *p;
 	const struct pll_rate_table *rate_set;
 	unsigned long old_rate;
+	unsigned int tmp;
 	int ret = 0;
 	u32 reg;
 	unsigned long flags = 0;
@@ -281,12 +282,14 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	reg = readl(pll->base + p->reg_off);
 
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
+	tmp = rate_set->n;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->m;
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
+	tmp = rate_set->m;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od;
@@ -298,20 +301,23 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		goto OUT;
 	}
 	reg = readl(pll->base + p->reg_off);
-	reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
+	tmp = rate_set->od;
+	reg = PARM_SET(p->width, p->shift, reg, tmp);
 	writel(reg, pll->base + p->reg_off);
 
 	p = &pll->od2;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
+		tmp = rate_set->od2;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
 	p = &pll->frac;
 	if (p->width) {
 		reg = readl(pll->base + p->reg_off);
-		reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
+		tmp = rate_set->frac;
+		reg = PARM_SET(p->width, p->shift, reg, tmp);
 		writel(reg, pll->base + p->reg_off);
 	}
 
-- 
2.7.4