From e2eb8e38592f28d8be4a518f44d3385272dedddb Mon Sep 17 00:00:00 2001 From: Benjamin Li Date: Fri, 8 Jan 2010 00:51:21 -0800 Subject: [PATCH] bnx2: Flush the register writes which setup the MSI-X table The MSI-X table size needs to be properly set before pci_enable_msix() is called. But on certain machines, the writes are delayed and the MSI-X table size is incorrectly read. By reading the BNX2_PCI_MSIX_CONTROL register, the writes are flushed and now ensure that the MSI-X table is set correctly before MSI-X is enable on the device. This patch was originally diagnosed and authored by Kalyan Ram Chintalapati . Signed-off-by: Benjamin Li Signed-off-by: Kalyan Ram Chintalapati Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/bnx2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 65df1de..b1c20e5 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -6145,6 +6145,10 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); + /* Need to flush the previous three writes to ensure MSI-X + * is setup properly */ + REG_RD(bp, BNX2_PCI_MSIX_CONTROL); + for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { msix_ent[i].entry = i; msix_ent[i].vector = 0; -- 2.7.4