From e2e9dd44f42261445d1af87624cedb3d09d63600 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sun, 2 May 2021 03:51:29 +0200 Subject: [PATCH] ac/surface: Handle non-retiled displayable DCC correctly for modifiers. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit There is some hardware with num_render_backends == 1, but the number of render backends in GB_ADDR_CFG > 1. Turns out this can be turned off by making them rb unaligned which is valid with only 1 render backend. Fixes: 0833dd7d124 ("amd/common: Add support for modifiers.") Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_surface.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index e638511..9b9e4dd 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -119,13 +119,18 @@ ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf, { assert(ac_modifier_has_dcc(modifier)); - surf_info->flags.metaRbUnaligned = 0; if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { surf_info->flags.metaPipeUnaligned = 0; } else { surf_info->flags.metaPipeUnaligned = !AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); } + /* The metaPipeUnaligned is not strictly necessary, but ensure we don't set metaRbUnaligned on + * non-displayable DCC surfaces just because num_render_backends = 1 */ + surf_info->flags.metaRbUnaligned = AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && + AMD_FMT_MOD_GET(RB, modifier) == 0 && + surf_info->flags.metaPipeUnaligned; + surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); @@ -218,22 +223,23 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, info->has_dcc_constant_encode) | AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | - AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | - AMD_FMT_MOD_SET(RB, rb); + AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits); ADD_MOD(AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1) | common_dcc | - AMD_FMT_MOD_SET(PIPE, pipes)) + AMD_FMT_MOD_SET(PIPE, pipes) | + AMD_FMT_MOD_SET(RB, rb)) ADD_MOD(AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1) | common_dcc | - AMD_FMT_MOD_SET(PIPE, pipes)) + AMD_FMT_MOD_SET(PIPE, pipes) | + AMD_FMT_MOD_SET(RB, rb)) if (util_format_get_blocksizebits(format) == 32) { if (info->max_render_backends == 1) { @@ -249,7 +255,8 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | AMD_FMT_MOD_SET(DCC_RETILE, 1) | common_dcc | - AMD_FMT_MOD_SET(PIPE, pipes)) + AMD_FMT_MOD_SET(PIPE, pipes) | + AMD_FMT_MOD_SET(RB, rb)) } -- 2.7.4