From e1bd5d8bc13f51c7c991f04255b3868e31933252 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 17 Jul 2012 15:18:31 +0800 Subject: [PATCH] powerpc/85xx: P3041DS - change espi input-clock from 40MHz to 35MHz Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi cannot work at 40MHz with this CCB frequency, so we need to slow down the clock rate of espi to 35MHz to make it work stable at the CCB frequency. Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p3041ds.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts index 22a215e..6cdcadc 100644 --- a/arch/powerpc/boot/dts/p3041ds.dts +++ b/arch/powerpc/boot/dts/p3041ds.dts @@ -58,7 +58,7 @@ #size-cells = <1>; compatible = "spansion,s25sl12801"; reg = <0>; - spi-max-frequency = <40000000>; /* input clock */ + spi-max-frequency = <35000000>; /* input clock */ partition@u-boot { label = "u-boot"; reg = <0x00000000 0x00100000>; -- 2.7.4