From e1aa91b36325086164b2dffd761b6d3960e40171 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 26 May 2023 14:39:57 +0200 Subject: [PATCH] [InstCombine] Use KnownBits::shl() in SimplifyDemandedBits() It is more precise than the custom logic we had. This came up when trying to enforce a consistency assertion with computeKnownBits(). --- .../InstCombine/InstCombineSimplifyDemanded.cpp | 22 ++++------------------ .../canonicalize-ashr-shl-to-masking.ll | 2 +- .../canonicalize-lshr-shl-to-masking.ll | 2 +- .../Transforms/InstCombine/select-obo-peo-ops.ll | 12 ++---------- 4 files changed, 8 insertions(+), 30 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index ad30309..3e0c024 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -644,24 +644,10 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, return I; assert(!Known.hasConflict() && "Bits known to be one AND zero?"); - bool SignBitZero = Known.Zero.isSignBitSet(); - bool SignBitOne = Known.One.isSignBitSet(); - Known.Zero <<= ShiftAmt; - Known.One <<= ShiftAmt; - // low bits known zero. - if (ShiftAmt) - Known.Zero.setLowBits(ShiftAmt); - - // If this shift has "nsw" keyword, then the result is either a poison - // value or has the same sign bit as the first operand. - if (IOp->hasNoSignedWrap()) { - if (SignBitZero) - Known.Zero.setSignBit(); - else if (SignBitOne) - Known.One.setSignBit(); - if (Known.hasConflict()) - return PoisonValue::get(VTy); - } + Known = KnownBits::shl(Known, + KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)), + /* NUW */ IOp->hasNoUnsignedWrap(), + /* NSW */ IOp->hasNoSignedWrap()); } else { // This is a variable shift, so we can't shift the demand mask by a known // amount. But if we are not demanding high bits, then we are not diff --git a/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll b/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll index bace0b2..00e2bdf 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll @@ -189,7 +189,7 @@ define i8 @positive_biggerashr_shlnuwnsw(i8 %x) { define i8 @positive_biggershl_shlnuwnsw(i8 %x) { ; CHECK-LABEL: @positive_biggershl_shlnuwnsw( ; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i8 [[X:%.*]], 3 -; CHECK-NEXT: [[RET:%.*]] = and i8 [[TMP1]], -64 +; CHECK-NEXT: [[RET:%.*]] = and i8 [[TMP1]], 64 ; CHECK-NEXT: ret i8 [[RET]] ; %tmp0 = ashr i8 %x, 3 diff --git a/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll b/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll index ecdc00a3..0b8165e 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll @@ -189,7 +189,7 @@ define i8 @positive_biggerlshr_shlnuwnsw(i8 %x) { define i8 @positive_biggershl_shlnuwnsw(i8 %x) { ; CHECK-LABEL: @positive_biggershl_shlnuwnsw( ; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i8 [[X:%.*]], 3 -; CHECK-NEXT: [[RET:%.*]] = and i8 [[TMP1]], -64 +; CHECK-NEXT: [[RET:%.*]] = and i8 [[TMP1]], 64 ; CHECK-NEXT: ret i8 [[RET]] ; %t0 = lshr i8 %x, 3 diff --git a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll index 82ef5d7..5e3950c 100644 --- a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll +++ b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll @@ -139,11 +139,7 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) { define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) { ; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe( -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 -; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] -; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] -; CHECK-NEXT: ret i32 [[TMP4]] +; CHECK-NEXT: ret i32 0 ; %1 = or i32 %x, -83886080 %2 = icmp eq i32 %1, -83886079 @@ -156,11 +152,7 @@ define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) { define i32 @test_shl_nuw__nsw_is_safe(i32 %x) { ; CHECK-LABEL: @test_shl_nuw__nsw_is_safe( -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 -; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] -; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] -; CHECK-NEXT: ret i32 [[TMP4]] +; CHECK-NEXT: ret i32 0 ; %1 = or i32 %x, -83886080 %2 = icmp eq i32 %1, -83886079 -- 2.7.4