From e198f3a6d754ab0f49654000cd701c1e148454ef Mon Sep 17 00:00:00 2001 From: Philipp Hortmann Date: Fri, 20 Jan 2023 21:18:02 +0100 Subject: [PATCH] staging: rtl8192e: Init tx_pwr_level_cck_a and friends directly The arrays EEPROMRfACCKChnl1TxPwLevel, EEPROMRfAOfdmChnlTxPwLevel, EEPROMRfCCCKChnl1TxPwLevel, EEPROMRfCOfdmChnlTxPwLevel are initialized to zero and never changed. Delete the arrays and set the variables directly to zero to avoid CamelCase which is not accepted by checkpatch. Signed-off-by: Philipp Hortmann Link: https://lore.kernel.org/r/9874e99fb9a803be2a89e81e2ecd01ba80398ea1.1674244819.git.philipp.g.hortmann@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c | 12 ++++-------- drivers/staging/rtl8192e/rtl8192e/rtl_core.h | 4 ---- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c index 7187ee4..fdf37c5 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c @@ -427,14 +427,10 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) } else if (priv->epromtype == EEPROM_93C56) { for (i = 0; i < 14; i++) { - priv->tx_pwr_level_cck_a[i] = - priv->EEPROMRfACCKChnl1TxPwLevel[0]; - priv->tx_pwr_level_ofdm_24g_a[i] = - priv->EEPROMRfAOfdmChnlTxPwLevel[0]; - priv->tx_pwr_level_cck_c[i] = - priv->EEPROMRfCCCKChnl1TxPwLevel[0]; - priv->tx_pwr_level_ofdm_24g_c[i] = - priv->EEPROMRfCOfdmChnlTxPwLevel[0]; + priv->tx_pwr_level_cck_a[i] = 0; + priv->tx_pwr_level_ofdm_24g_a[i] = 0; + priv->tx_pwr_level_cck_c[i] = 0; + priv->tx_pwr_level_ofdm_24g_c[i] = 0; } priv->legacy_ht_tx_pwr_diff = priv->eeprom_legacy_ht_tx_pwr_diff; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h index 11f3f88..596693f 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -423,10 +423,6 @@ struct r8192_priv { u8 eeprom_tx_pwr_level_cck[14]; u8 eeprom_tx_pwr_level_ofdm24g[14]; - u8 EEPROMRfACCKChnl1TxPwLevel[3]; - u8 EEPROMRfAOfdmChnlTxPwLevel[3]; - u8 EEPROMRfCCCKChnl1TxPwLevel[3]; - u8 EEPROMRfCOfdmChnlTxPwLevel[3]; u16 eeprom_ant_pwr_diff; u8 eeprom_thermal_meter; u8 eeprom_crystal_cap; -- 2.7.4