From e187cd32736c4dec81e7ec6da81dbb75d48824d3 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Sun, 22 Apr 2018 14:19:37 +0000 Subject: [PATCH] [InstSimplify, InstCombine] add vector tests with undef elts; NFC llvm-svn: 330543 --- llvm/test/Transforms/InstCombine/min-positive.ll | 34 ++++++++---- llvm/test/Transforms/InstSimplify/AndOrXor.ll | 67 +++++++++++++++--------- llvm/test/Transforms/InstSimplify/shift.ll | 18 +++++++ 3 files changed, 85 insertions(+), 34 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/min-positive.ll b/llvm/test/Transforms/InstCombine/min-positive.ll index c82e51a..618795e 100644 --- a/llvm/test/Transforms/InstCombine/min-positive.ll +++ b/llvm/test/Transforms/InstCombine/min-positive.ll @@ -5,7 +5,7 @@ define i1 @smin(i32 %other) { ; CHECK-LABEL: @smin( -; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 %other, 0 +; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 [[OTHER:%.*]], 0 ; CHECK-NEXT: ret i1 [[TEST]] ; %positive = load i32, i32* @g, !range !{i32 1, i32 2048} @@ -19,7 +19,7 @@ define i1 @smin(i32 %other) { define <2 x i1> @smin_vec(<2 x i32> %x, <2 x i32> %other) { ; CHECK-LABEL: @smin_vec( -; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> %other, zeroinitializer +; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[OTHER:%.*]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TEST]] ; %notneg = and <2 x i32> %x, @@ -32,7 +32,7 @@ define <2 x i1> @smin_vec(<2 x i32> %x, <2 x i32> %other) { define i1 @smin_commute(i32 %other) { ; CHECK-LABEL: @smin_commute( -; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 %other, 0 +; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 [[OTHER:%.*]], 0 ; CHECK-NEXT: ret i1 [[TEST]] ; %positive = load i32, i32* @g, !range !{i32 1, i32 2048} @@ -44,7 +44,7 @@ define i1 @smin_commute(i32 %other) { define <2 x i1> @smin_commute_vec(<2 x i32> %x, <2 x i32> %other) { ; CHECK-LABEL: @smin_commute_vec( -; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> %other, zeroinitializer +; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[OTHER:%.*]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TEST]] ; %notneg = and <2 x i32> %x, @@ -55,13 +55,29 @@ define <2 x i1> @smin_commute_vec(<2 x i32> %x, <2 x i32> %other) { ret <2 x i1> %test } +define <2 x i1> @smin_commute_vec_undef_elts(<2 x i32> %x, <2 x i32> %other) { +; CHECK-LABEL: @smin_commute_vec_undef_elts( +; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[POSITIVE:%.*]] = or <2 x i32> [[NOTNEG]], +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[POSITIVE]], [[OTHER:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[OTHER]], <2 x i32> [[POSITIVE]] +; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], +; CHECK-NEXT: ret <2 x i1> [[TEST]] +; + %notneg = and <2 x i32> %x, + %positive = or <2 x i32> %notneg, + %cmp = icmp slt <2 x i32> %other, %positive + %sel = select <2 x i1> %cmp, <2 x i32> %other, <2 x i32> %positive + %test = icmp sgt <2 x i32> %sel, + ret <2 x i1> %test +} ; %positive might be zero define i1 @maybe_not_positive(i32 %other) { ; CHECK-LABEL: @maybe_not_positive( ; CHECK-NEXT: [[POSITIVE:%.*]] = load i32, i32* @g, align 4, !range !0 -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[POSITIVE]], %other -; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[POSITIVE]], i32 %other +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[POSITIVE]], [[OTHER:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[POSITIVE]], i32 [[OTHER]] ; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 [[SEL]], 0 ; CHECK-NEXT: ret i1 [[TEST]] ; @@ -74,9 +90,9 @@ define i1 @maybe_not_positive(i32 %other) { define <2 x i1> @maybe_not_positive_vec(<2 x i32> %x, <2 x i32> %other) { ; CHECK-LABEL: @maybe_not_positive_vec( -; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> %x, -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[NOTNEG]], %other -; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[NOTNEG]], <2 x i32> %other +; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[NOTNEG]], [[OTHER:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[NOTNEG]], <2 x i32> [[OTHER]] ; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TEST]] ; diff --git a/llvm/test/Transforms/InstSimplify/AndOrXor.ll b/llvm/test/Transforms/InstSimplify/AndOrXor.ll index 70c7660..859e763 100644 --- a/llvm/test/Transforms/InstSimplify/AndOrXor.ll +++ b/llvm/test/Transforms/InstSimplify/AndOrXor.ll @@ -1,6 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instsimplify -S | FileCheck %s +define i8 @and0(i8 %x) { +; CHECK-LABEL: @and0( +; CHECK-NEXT: ret i8 0 +; + %r = and i8 %x, 0 + ret i8 %r +} + +define <2 x i8> @and0_vec_undef_elt(<2 x i8> %x) { +; CHECK-LABEL: @and0_vec_undef_elt( +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[X:%.*]], +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %r = and <2 x i8> %x, + ret <2 x i8> %r +} + ; add nsw (xor X, signbit), signbit --> X define <2 x i32> @add_nsw_signbit(<2 x i32> %x) { @@ -47,8 +64,8 @@ define <2 x i5> @add_nuw_signbit_undef(<2 x i5> %x) { define i64 @pow2(i32 %x) { ; CHECK-LABEL: @pow2( -; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, %x -; CHECK-NEXT: [[X2:%.*]] = and i32 %x, [[NEGX]] +; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]] +; CHECK-NEXT: [[X2:%.*]] = and i32 [[X]], [[NEGX]] ; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64 ; CHECK-NEXT: ret i64 [[E]] ; @@ -62,7 +79,7 @@ define i64 @pow2(i32 %x) { define i64 @pow2b(i32 %x) { ; CHECK-LABEL: @pow2b( -; CHECK-NEXT: [[SH:%.*]] = shl i32 2, %x +; CHECK-NEXT: [[SH:%.*]] = shl i32 2, [[X:%.*]] ; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64 ; CHECK-NEXT: ret i64 [[E]] ; @@ -347,7 +364,7 @@ define i32 @neg_nuw(i32 %x) { define i1 @and_icmp1(i32 %x, i32 %y) { ; CHECK-LABEL: @and_icmp1( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %x, %y +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: ret i1 [[TMP1]] ; %1 = icmp ult i32 %x, %y @@ -368,7 +385,7 @@ define i1 @and_icmp2(i32 %x, i32 %y) { define i1 @or_icmp1(i32 %x, i32 %y) { ; CHECK-LABEL: @or_icmp1( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %y, 0 +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0 ; CHECK-NEXT: ret i1 [[TMP1]] ; %1 = icmp ult i32 %x, %y @@ -389,7 +406,7 @@ define i1 @or_icmp2(i32 %x, i32 %y) { define i1 @or_icmp3(i32 %x, i32 %y) { ; CHECK-LABEL: @or_icmp3( -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 %x, %y +; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: ret i1 [[TMP1]] ; %1 = icmp uge i32 %x, %y @@ -458,9 +475,9 @@ define i3 @and_of_bitcast_icmps_vec(<3 x i65> %i) { define i16 @and_of_different_cast_icmps(i8 %i) { ; CHECK-LABEL: @and_of_different_cast_icmps( -; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 %i, 0 +; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 [[I:%.*]], 0 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16 -; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %i, 1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[I]], 1 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16 ; CHECK-NEXT: [[AND:%.*]] = and i16 [[CONV0]], [[CONV1]] ; CHECK-NEXT: ret i16 [[AND]] @@ -475,9 +492,9 @@ define i16 @and_of_different_cast_icmps(i8 %i) { define <2 x i3> @and_of_different_cast_icmps_vec(<2 x i8> %i, <2 x i16> %j) { ; CHECK-LABEL: @and_of_different_cast_icmps_vec( -; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> %i, zeroinitializer +; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> [[I:%.*]], zeroinitializer ; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3> -; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> %j, +; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> [[J:%.*]], ; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3> ; CHECK-NEXT: [[AND:%.*]] = and <2 x i3> [[CONV0]], [[CONV1]] ; CHECK-NEXT: ret <2 x i3> [[AND]] @@ -520,9 +537,9 @@ define i3 @or_of_bitcast_icmps_vec(<3 x i65> %i) { define i16 @or_of_different_cast_icmps(i8 %i) { ; CHECK-LABEL: @or_of_different_cast_icmps( -; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i8 %i, 0 +; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i8 [[I:%.*]], 0 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16 -; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 %i, 1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[I]], 1 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[CONV0]], [[CONV1]] ; CHECK-NEXT: ret i16 [[OR]] @@ -539,8 +556,8 @@ define i16 @or_of_different_cast_icmps(i8 %i) { define i32 @test43(i32 %a, i32 %b) { ; CHECK-LABEL: @test43( -; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b -; CHECK-NEXT: ret i32 [[OR]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[XOR]] ; %neg = xor i32 %b, -1 %and = and i32 %a, %neg @@ -551,8 +568,8 @@ define i32 @test43(i32 %a, i32 %b) { define i32 @test43_commuted_and(i32 %a, i32 %b) { ; CHECK-LABEL: @test43_commuted_and( -; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b -; CHECK-NEXT: ret i32 [[OR]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[XOR]] ; %neg = xor i32 %b, -1 %and = and i32 %neg, %a @@ -566,8 +583,8 @@ define i32 @test43_commuted_and(i32 %a, i32 %b) { define i32 @test44(i32 %a, i32 %b) { ; CHECK-LABEL: @test44( -; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b -; CHECK-NEXT: ret i32 [[OR]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[XOR]] ; %xor = xor i32 %a, %b %neg = xor i32 %b, -1 @@ -578,8 +595,8 @@ define i32 @test44(i32 %a, i32 %b) { define i32 @test44_commuted_and(i32 %a, i32 %b) { ; CHECK-LABEL: @test44_commuted_and( -; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b -; CHECK-NEXT: ret i32 [[OR]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[XOR]] ; %xor = xor i32 %a, %b %neg = xor i32 %b, -1 @@ -827,7 +844,7 @@ define i32 @test58(i32 %a, i32 %b) { define i8 @lshr_perfect_mask(i8 %x) { ; CHECK-LABEL: @lshr_perfect_mask( -; CHECK-NEXT: [[SH:%.*]] = lshr i8 %x, 5 +; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5 ; CHECK-NEXT: ret i8 [[SH]] ; %sh = lshr i8 %x, 5 @@ -837,7 +854,7 @@ define i8 @lshr_perfect_mask(i8 %x) { define <2 x i8> @lshr_oversized_mask_splat(<2 x i8> %x) { ; CHECK-LABEL: @lshr_oversized_mask_splat( -; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> %x, +; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[X:%.*]], ; CHECK-NEXT: ret <2 x i8> [[SH]] ; %sh = lshr <2 x i8> %x, @@ -847,7 +864,7 @@ define <2 x i8> @lshr_oversized_mask_splat(<2 x i8> %x) { define i8 @lshr_undersized_mask(i8 %x) { ; CHECK-LABEL: @lshr_undersized_mask( -; CHECK-NEXT: [[SH:%.*]] = lshr i8 %x, 5 +; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SH]], -2 ; CHECK-NEXT: ret i8 [[MASK]] ; @@ -858,7 +875,7 @@ define i8 @lshr_undersized_mask(i8 %x) { define <2 x i8> @shl_perfect_mask_splat(<2 x i8> %x) { ; CHECK-LABEL: @shl_perfect_mask_splat( -; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> %x, +; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], ; CHECK-NEXT: ret <2 x i8> [[SH]] ; %sh = shl <2 x i8> %x, @@ -868,7 +885,7 @@ define <2 x i8> @shl_perfect_mask_splat(<2 x i8> %x) { define i8 @shl_oversized_mask(i8 %x) { ; CHECK-LABEL: @shl_oversized_mask( -; CHECK-NEXT: [[SH:%.*]] = shl i8 %x, 6 +; CHECK-NEXT: [[SH:%.*]] = shl i8 [[X:%.*]], 6 ; CHECK-NEXT: ret i8 [[SH]] ; %sh = shl i8 %x, 6 diff --git a/llvm/test/Transforms/InstSimplify/shift.ll b/llvm/test/Transforms/InstSimplify/shift.ll index 770b7a8..87b3e82 100644 --- a/llvm/test/Transforms/InstSimplify/shift.ll +++ b/llvm/test/Transforms/InstSimplify/shift.ll @@ -17,6 +17,15 @@ define i41 @shl_0(i41 %X) { ret i41 %B } +define <2 x i41> @shl_0_vec_undef_elt(<2 x i41> %X) { +; CHECK-LABEL: @shl_0_vec_undef_elt( +; CHECK-NEXT: [[B:%.*]] = shl <2 x i41> , [[X:%.*]] +; CHECK-NEXT: ret <2 x i41> [[B]] +; + %B = shl <2 x i41> , %X + ret <2 x i41> %B +} + define i41 @ashr_by_0(i41 %A) { ; CHECK-LABEL: @ashr_by_0( ; CHECK-NEXT: ret i41 [[A:%.*]] @@ -33,6 +42,15 @@ define i39 @ashr_0(i39 %X) { ret i39 %B } +define <2 x i141> @ashr_0_vec_undef_elt(<2 x i141> %X) { +; CHECK-LABEL: @ashr_0_vec_undef_elt( +; CHECK-NEXT: [[B:%.*]] = shl <2 x i141> , [[X:%.*]] +; CHECK-NEXT: ret <2 x i141> [[B]] +; + %B = shl <2 x i141> , %X + ret <2 x i141> %B +} + define i55 @lshr_by_bitwidth(i55 %A) { ; CHECK-LABEL: @lshr_by_bitwidth( ; CHECK-NEXT: ret i55 undef -- 2.7.4