From e10123abbc5db588923f5790f73e703f61b96a81 Mon Sep 17 00:00:00 2001 From: "xingyu.wu" Date: Thu, 23 Jun 2022 15:47:49 +0800 Subject: [PATCH] spi:Modify pl022 driver format Signed-off-by: Xingyu Wu --- drivers/spi/spi-pl022-starfive.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-pl022-starfive.c b/drivers/spi/spi-pl022-starfive.c index 8ea376d..6a25d52 100755 --- a/drivers/spi/spi-pl022-starfive.c +++ b/drivers/spi/spi-pl022-starfive.c @@ -42,7 +42,7 @@ * val shifted sb steps to the left. */ #define SSP_WRITE_BITS(reg, val, mask, sb) \ - ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) + ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) /* * This macro is also used to define some default values. @@ -50,7 +50,7 @@ * the result with mask. */ #define GEN_MASK_BITS(val, mask, sb) \ - (((val)<<(sb)) & (mask)) + (((val)<<(sb)) & (mask)) #define DRIVE_TX 0 #define DO_NOT_DRIVE_TX 1 @@ -477,6 +477,7 @@ static void pl022_cs_control(struct pl022 *pl022, u32 command) static void giveback(struct pl022 *pl022) { struct spi_transfer *last_transfer; + pl022->next_msg_cs_active = false; last_transfer = list_last_entry(&pl022->cur_msg->transfers, @@ -537,7 +538,7 @@ static int flush(struct pl022 *pl022) { unsigned long limit = loops_per_jiffy << 1; - dev_dbg(&pl022->adev->dev, "flush\n"); + dev_dbg(&pl022->adev->dev, "%s\n", __func__); do { while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) readw(SSP_DR(pl022->virtbase)); @@ -1573,7 +1574,6 @@ out: message->status = -EIO; giveback(pl022); - return; } static int pl022_transfer_one_message(struct spi_master *master, @@ -1798,7 +1798,7 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct scr = SCR_MIN; } - WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", + WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate\n", freq); clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); @@ -1904,8 +1904,8 @@ static int pl022_setup(struct spi_device *spi) * We can override with custom divisors, else we use the board * frequency setting */ - if ((0 == chip_info->clk_freq.cpsdvsr) - && (0 == chip_info->clk_freq.scr)) { + if ((chip_info->clk_freq.cpsdvsr == 0) + && (chip_info->clk_freq.scr == 0)) { status = calculate_effective_freq(pl022, spi->max_speed_hz, &clk_freq); -- 2.7.4