From e07fe890353dce5fbefb0e03856f7faabfac06cb Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Wed, 26 Jul 2017 21:13:03 -0700 Subject: [PATCH] i965: Hide the register type hardware encodings So we stop mixing them with the logical enum. Reviewed-by: Scott D Phillips --- src/intel/compiler/brw_eu_defines.h | 31 ------------------------------- src/intel/compiler/brw_reg_type.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 44bde3f..da482b7 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -819,37 +819,6 @@ enum PACKED brw_reg_file { BAD_FILE, }; -enum hw_reg_type { - BRW_HW_REG_TYPE_UD = 0, - BRW_HW_REG_TYPE_D = 1, - BRW_HW_REG_TYPE_UW = 2, - BRW_HW_REG_TYPE_W = 3, - BRW_HW_REG_TYPE_F = 7, - GEN8_HW_REG_TYPE_UQ = 8, - GEN8_HW_REG_TYPE_Q = 9, - - BRW_HW_REG_TYPE_UB = 4, - BRW_HW_REG_TYPE_B = 5, - GEN7_HW_REG_TYPE_DF = 6, - GEN8_HW_REG_TYPE_HF = 10, -}; - -enum hw_imm_type { - BRW_HW_IMM_TYPE_UD = 0, - BRW_HW_IMM_TYPE_D = 1, - BRW_HW_IMM_TYPE_UW = 2, - BRW_HW_IMM_TYPE_W = 3, - BRW_HW_IMM_TYPE_F = 7, - GEN8_HW_IMM_TYPE_UQ = 8, - GEN8_HW_IMM_TYPE_Q = 9, - - BRW_HW_IMM_TYPE_UV = 4, /* Gen6+ packed unsigned immediate vector */ - BRW_HW_IMM_TYPE_VF = 5, /* packed float immediate vector */ - BRW_HW_IMM_TYPE_V = 6, /* packed int imm. vector; uword dest only */ - GEN8_HW_IMM_TYPE_DF = 10, - GEN8_HW_IMM_TYPE_HF = 11, -}; - /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so * the types were implied. IVB adds BFE and BFI2 that operate on doublewords * and unsigned doublewords, so a new field is also available in the da3src diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index e2f4d35..a0f674f 100644 --- a/src/intel/compiler/brw_reg_type.c +++ b/src/intel/compiler/brw_reg_type.c @@ -27,6 +27,37 @@ #define INVALID (-1) +enum hw_reg_type { + BRW_HW_REG_TYPE_UD = 0, + BRW_HW_REG_TYPE_D = 1, + BRW_HW_REG_TYPE_UW = 2, + BRW_HW_REG_TYPE_W = 3, + BRW_HW_REG_TYPE_F = 7, + GEN8_HW_REG_TYPE_UQ = 8, + GEN8_HW_REG_TYPE_Q = 9, + + BRW_HW_REG_TYPE_UB = 4, + BRW_HW_REG_TYPE_B = 5, + GEN7_HW_REG_TYPE_DF = 6, + GEN8_HW_REG_TYPE_HF = 10, +}; + +enum hw_imm_type { + BRW_HW_IMM_TYPE_UD = 0, + BRW_HW_IMM_TYPE_D = 1, + BRW_HW_IMM_TYPE_UW = 2, + BRW_HW_IMM_TYPE_W = 3, + BRW_HW_IMM_TYPE_F = 7, + GEN8_HW_IMM_TYPE_UQ = 8, + GEN8_HW_IMM_TYPE_Q = 9, + + BRW_HW_IMM_TYPE_UV = 4, + BRW_HW_IMM_TYPE_VF = 5, + BRW_HW_IMM_TYPE_V = 6, + GEN8_HW_IMM_TYPE_DF = 10, + GEN8_HW_IMM_TYPE_HF = 11, +}; + static const struct { enum hw_reg_type reg_type; enum hw_imm_type imm_type; -- 2.7.4