From e077367a28102128483f4b2555d2ad31e21b1965 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Fri, 18 Sep 2020 08:39:31 +0100 Subject: [PATCH] [SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits An existing function Type::getScalarSizeInBits returns a uint64_t instead of a TypeSize class because the caller is requesting a scalar size, which cannot be scalable. This patch makes other similar functions requesting a scalar size consistent with that, thereby eliminating more than 1000 implicit TypeSize -> uint64_t casts. Differential revision: https://reviews.llvm.org/D87889 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 4 ++-- llvm/include/llvm/CodeGen/ValueTypes.h | 4 ++-- llvm/include/llvm/Support/MachineValueType.h | 4 ++-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++-- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 ++-- llvm/lib/CodeGen/TargetLoweringBase.cpp | 5 ++--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- 8 files changed, 15 insertions(+), 16 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index fa15083..d93e2f9 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -180,8 +180,8 @@ public: return getValueType().getSizeInBits(); } - TypeSize getScalarValueSizeInBits() const { - return getValueType().getScalarType().getSizeInBits(); + uint64_t getScalarValueSizeInBits() const { + return getValueType().getScalarType().getSizeInBits().getFixedSize(); } // Forwarding methods - These forward to the corresponding methods in SDNode. diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h index 2e172bf..ad4083d 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.h +++ b/llvm/include/llvm/CodeGen/ValueTypes.h @@ -318,8 +318,8 @@ namespace llvm { return getExtendedSizeInBits(); } - TypeSize getScalarSizeInBits() const { - return getScalarType().getSizeInBits(); + uint64_t getScalarSizeInBits() const { + return getScalarType().getSizeInBits().getFixedSize(); } /// Return the number of bytes overwritten by a store of the specified value diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h index d88efce..aa1c9c9 100644 --- a/llvm/include/llvm/Support/MachineValueType.h +++ b/llvm/include/llvm/Support/MachineValueType.h @@ -923,8 +923,8 @@ namespace llvm { } } - TypeSize getScalarSizeInBits() const { - return getScalarType().getSizeInBits(); + uint64_t getScalarSizeInBits() const { + return getScalarType().getSizeInBits().getFixedSize(); } /// Return the number of bytes overwritten by a store of the specified value diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 285bd24..e9e6a88 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5300,9 +5300,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // of the BuildVec must mask the bottom bits of the extended element // type if (ConstantSDNode *Splat = BVec->getConstantSplatNode()) { - TypeSize ElementSize = + uint64_t ElementSize = LoadVT.getVectorElementType().getScalarSizeInBits(); - if (Splat->getAPIntValue().isMask((uint64_t)ElementSize)) { + if (Splat->getAPIntValue().isMask(ElementSize)) { return DAG.getMaskedLoad( ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(), MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(), diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b9674c0..f511ec5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5340,8 +5340,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, // amounts. This catches things like trying to shift an i1024 value by an // i8, which is easy to fall into in generic code that uses // TLI.getShiftAmount(). - assert(N2.getValueType().getScalarSizeInBits().getFixedSize() >= - Log2_32_Ceil(VT.getScalarSizeInBits().getFixedSize()) && + assert(N2.getValueType().getScalarSizeInBits() >= + Log2_32_Ceil(VT.getScalarSizeInBits()) && "Invalid use of small shift amount with oversized value!"); // Always fold shifts of i1 values so the code generator doesn't need to diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 7ef37db..26ec3f1 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -993,7 +993,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, NewVT = EltTy; IntermediateVT = NewVT; - unsigned LaneSizeInBits = NewVT.getScalarSizeInBits().getFixedSize(); + unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); // Convert sizes such as i33 to i64. if (!isPowerOf2_32(LaneSizeInBits)) @@ -1002,8 +1002,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, MVT DestVT = TLI->getRegisterType(NewVT); RegisterVT = DestVT; if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. - return NumVectorRegs * - (LaneSizeInBits / DestVT.getScalarSizeInBits().getFixedSize()); + return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 56d4f00..95d8af7 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7440,8 +7440,8 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, // trunc. So only std::min(SrcBits, DestBits) actually get defined in this // segment. EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType(); - int BitsDefined = - std::min(OrigEltTy.getSizeInBits(), VT.getScalarSizeInBits()); + int BitsDefined = std::min(OrigEltTy.getScalarSizeInBits(), + VT.getScalarSizeInBits()); int LanesDefined = BitsDefined / BitsPerShuffleLane; // This source is expected to fill ResMultiplier lanes of the final shuffle, diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 3d67486..774f057 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -7845,7 +7845,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, // trunc. So only std::min(SrcBits, DestBits) actually get defined in this // segment. EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType(); - int BitsDefined = std::min(OrigEltTy.getSizeInBits(), + int BitsDefined = std::min(OrigEltTy.getScalarSizeInBits(), VT.getScalarSizeInBits()); int LanesDefined = BitsDefined / BitsPerShuffleLane; -- 2.7.4