From e073899ec3e14d3a9fe7ac62469c1768f4bb7fe0 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 3 Jan 2023 13:22:27 -0500 Subject: [PATCH] arm64: dts: qcom: sa8540p-ride: add i2c nodes Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-0 i2c Geni-I2C I2C adapter i2c-1 i2c Geni-I2C I2C adapter i2c-12 i2c Geni-I2C I2C adapter i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Signed-off-by: Brian Masney Reviewed-by: Konrad Dybcio Tested-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230103182229.37169-9-bmasney@redhat.com --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index b2d5dea..eacc176 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,6 +17,11 @@ compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c12 = &i2c12; + i2c15 = &i2c15; + i2c18 = &i2c18; serial0 = &uart17; }; @@ -146,6 +151,41 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + + status = "okay"; +}; + +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_default>; + + status = "okay"; +}; + +&i2c15 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c15_default>; + + status = "okay"; +}; + +&i2c18 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c18_default>; + + status = "okay"; +}; + &pcie2a { ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, @@ -188,6 +228,14 @@ status = "okay"; }; +&qup0 { + status = "okay"; +}; + +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -268,6 +316,41 @@ /* PINCTRL */ &tlmm { + i2c0_default: i2c0-default-state { + pins = "gpio135", "gpio136"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + pins = "gpio158", "gpio159"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + pins = "gpio0", "gpio1"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + pins = "gpio36", "gpio37"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + pins = "gpio66", "gpio67"; + function = "qup18"; + drive-strength = <2>; + bias-pull-up; + }; + pcie2a_default: pcie2a-default-state { perst-pins { pins = "gpio143"; -- 2.7.4