From e053f96a9f57bb73a47bdd96512ed1c83ff84c04 Mon Sep 17 00:00:00 2001 From: Jonathan Wright Date: Thu, 28 Jan 2021 12:46:37 +0000 Subject: [PATCH] aarch64: Use RTL builtins for [su]mlsl_lane[q] intrinsics Rewrite [su]mlsl_lane[q] Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-28 Jonathan Wright * config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_lane[q] builtin generator macros. * config/aarch64/aarch64-simd.md (aarch64_vec_mlsl_lane): Define. * config/aarch64/arm_neon.h (vmlsl_lane_s16): Use RTL builtin instead of inline asm. (vmlsl_lane_s32): Likewise. (vmlsl_lane_u16): Likewise. (vmlsl_lane_u32): Likewise. (vmlsl_laneq_s16): Likewise. (vmlsl_laneq_s32): Likewise. (vmlsl_laneq_u16): Likewise. (vmlsl_laneq_u32): Likewise. --- gcc/config/aarch64/aarch64-simd-builtins.def | 5 + gcc/config/aarch64/aarch64-simd.md | 20 ++++ gcc/config/aarch64/arm_neon.h | 156 +++++++++------------------ 3 files changed, 77 insertions(+), 104 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index cb79c08..4913231 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -264,6 +264,11 @@ BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, ALL) BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, ALL) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_laneq_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_laneq_, 0, NONE) + BUILTIN_VSD_HSI (BINOP, sqdmull, 0, NONE) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, NONE) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 919d0b0..adeec02 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2082,6 +2082,26 @@ [(set_attr "type" "neon_mla__scalar_long")] ) +(define_insn "aarch64_vec_mlsl_lane" + [(set (match_operand: 0 "register_operand" "=w") + (minus: + (match_operand: 1 "register_operand" "0") + (mult: + (ANY_EXTEND: + (match_operand: 2 "register_operand" "w")) + (ANY_EXTEND: + (vec_duplicate: + (vec_select: + (match_operand:VDQHS 3 "register_operand" "") + (parallel [(match_operand:SI 4 "immediate_operand" "i")])))))))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (mode, INTVAL (operands[4])); + return "mlsl\\t%0., %2., %3.[%4]"; + } + [(set_attr "type" "neon_mla__scalar_long")] +) + ;; FP vector operations. ;; AArch64 AdvSIMD supports single-precision (32-bit) and ;; double-precision (64-bit) floating-point data types and arithmetic as diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index b56ab68..2a71ca9 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8068,117 +8068,65 @@ vmlsl_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) return __builtin_aarch64_umlsl_hiv4si_uuuu (__a, __b, __c); } -#define vmlsl_lane_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x4_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_lane_v4hi (__a, __b, __v, __lane); +} -#define vmlsl_lane_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x2_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_lane_v2si (__a, __b, __v, __lane); +} -#define vmlsl_lane_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x4_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_lane_v4hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_lane_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x2_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_lane_v2si_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_laneq_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x8_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_laneq_v4hi (__a, __b, __v, __lane); +} -#define vmlsl_laneq_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x4_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_laneq_v2si (__a, __b, __v, __lane); +} -#define vmlsl_laneq_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x8_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_u16 (uint32x4_t __a, uint16x4_t __b, uint16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_laneq_v4hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_laneq_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x4_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_u32 (uint64x2_t __a, uint32x2_t __b, uint32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_laneq_v2si_uuuus (__a, __b, __v, __lane); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -- 2.7.4