From e02e51df5b19f084d0176feee6a483d98d5b8c69 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Tue, 7 Mar 2023 17:03:50 +0100 Subject: [PATCH] tu: C++-proofing: fix designator initializer order Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/vulkan/tu_android.c | 2 +- src/freedreno/vulkan/tu_clear_blit.c | 42 ++++---- src/freedreno/vulkan/tu_cmd_buffer.c | 16 +-- src/freedreno/vulkan/tu_descriptor_set.c | 6 +- src/freedreno/vulkan/tu_device.c | 148 +++++++++++++++------------- src/freedreno/vulkan/tu_dynamic_rendering.c | 2 +- src/freedreno/vulkan/tu_image.c | 4 +- src/freedreno/vulkan/tu_knl_drm_msm.c | 8 +- src/freedreno/vulkan/tu_knl_kgsl.c | 10 +- src/freedreno/vulkan/tu_pipeline.c | 47 ++++----- src/freedreno/vulkan/tu_query.c | 4 +- src/freedreno/vulkan/tu_shader.c | 79 +++++++-------- 12 files changed, 192 insertions(+), 176 deletions(-) diff --git a/src/freedreno/vulkan/tu_android.c b/src/freedreno/vulkan/tu_android.c index 1029557..9def971 100644 --- a/src/freedreno/vulkan/tu_android.c +++ b/src/freedreno/vulkan/tu_android.c @@ -256,8 +256,8 @@ tu_import_memory_from_gralloc_handle(VkDevice device_h, const VkMemoryDedicatedAllocateInfo ded_alloc = { .sType = VK_STRUCTURE_TYPE_MEMORY_DEDICATED_ALLOCATE_INFO, .pNext = NULL, + .image = image_h, .buffer = VK_NULL_HANDLE, - .image = image_h }; const VkImportMemoryFdInfoKHR import_info = { diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index 4d083ae..f8d620b 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -413,11 +413,11 @@ r2d_setup_common(struct tu_cmd_buffer *cmd, tu_cs_emit(cs, unknown_8c01); uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL( - .scissor = scissor, .rotate = (enum a6xx_rotation) blit_param, .solid_color = clear, - .d24s8 = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear, .color_format = fmt, + .scissor = scissor, + .d24s8 = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear, .mask = 0xf, .ifmt = util_format_is_srgb(dst_format) ? R2D_UNORM8_SRGB : ifmt, ).value; @@ -722,9 +722,9 @@ compile_shader(struct tu_device *dev, struct nir_shader *nir, struct ir3_shader *sh = ir3_shader_from_nir(dev->compiler, nir, &(struct ir3_shader_options) { + .reserved_user_consts = align(consts, 4), .api_wavesize = IR3_SINGLE_OR_DOUBLE, .real_wavesize = IR3_SINGLE_OR_DOUBLE, - .reserved_user_consts = align(consts, 4), }, NULL); struct ir3_shader_key key = {}; @@ -800,11 +800,11 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, + .gfx_ibo = true, .gfx_shared_const = true, - .gfx_bindless = 0x1f, - .cs_bindless = 0x1f)); + .cs_bindless = 0x1f, + .gfx_bindless = 0x1f,)); tu6_emit_xs_config(cs, MESA_SHADER_VERTEX, vs); tu6_emit_xs_config(cs, MESA_SHADER_TESS_CTRL, NULL); @@ -843,10 +843,10 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, tu_cs_emit_regs(cs, A6XX_GRAS_CL_CNTL( - .persp_division_disable = 1, - .vp_xform_disable = 1, + .clip_disable = 1, .vp_clip_code_ignore = 1, - .clip_disable = 1)); + .vp_xform_disable = 1, + .persp_division_disable = 1,)); tu_cs_emit_regs(cs, A6XX_GRAS_SU_CNTL()); // XXX msaa enable? tu_cs_emit_regs(cs, A6XX_PC_RASTER_CNTL()); @@ -1551,14 +1551,14 @@ tu_image_view_copy_blit(struct fdl6_view *iview, fdl6_view_init(iview, &layout, &(struct fdl_view_args) { .iova = image->iova, - .base_array_layer = subres->baseArrayLayer + layer, - .layer_count = 1, .base_miplevel = subres->mipLevel, .level_count = 1, - .format = tu_format_for_aspect(format, aspect_mask), + .base_array_layer = subres->baseArrayLayer + layer, + .layer_count = 1, .swiz = { PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W }, + .format = tu_format_for_aspect(format, aspect_mask), .type = z_scale ? FDL_VIEW_TYPE_3D : FDL_VIEW_TYPE_2D, }, false); } @@ -2076,12 +2076,12 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd, const struct fdl_layout *staging_layout_ptr = &staging_layout; fdl6_view_init(&staging, &staging_layout_ptr, &(struct fdl_view_args) { .iova = staging_bo->iova, - .base_array_layer = 0, - .layer_count = 1, .base_miplevel = 0, .level_count = info->srcSubresource.layerCount, - .format = tu_format_for_aspect(src_format, VK_IMAGE_ASPECT_COLOR_BIT), + .base_array_layer = 0, + .layer_count = 1, .swiz = { PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W }, + .format = tu_format_for_aspect(src_format, VK_IMAGE_ASPECT_COLOR_BIT), .type = FDL_VIEW_TYPE_2D, }, false); @@ -2104,12 +2104,12 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd, fdl6_view_init(&staging, &staging_layout_ptr, &(struct fdl_view_args) { .iova = staging_bo->iova, - .base_array_layer = 0, - .layer_count = 1, .base_miplevel = 0, .level_count = info->srcSubresource.layerCount, - .format = tu_format_for_aspect(dst_format, VK_IMAGE_ASPECT_COLOR_BIT), + .base_array_layer = 0, + .layer_count = 1, .swiz = { PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W }, + .format = tu_format_for_aspect(dst_format, VK_IMAGE_ASPECT_COLOR_BIT), .type = FDL_VIEW_TYPE_2D, }, false); @@ -3066,9 +3066,9 @@ tu_emit_blit(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO( .unk0 = !resolve, .gmem = !resolve, - .depth = vk_format_is_depth_or_stencil(attachment->format), .sample_0 = vk_format_is_int(attachment->format) || - vk_format_is_depth_or_stencil(attachment->format))); + vk_format_is_depth_or_stencil(attachment->format), + .depth = vk_format_is_depth_or_stencil(attachment->format),)); for_each_layer(i, attachment->clear_views, cmd->state.framebuffer->layers) { tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4); @@ -3263,8 +3263,8 @@ store_cp_blit(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_SP_PS_2D_SRC_INFO( .color_format = fmt, - .color_swap = WZYX, .tile_mode = TILE6_2, + .color_swap = WZYX, .srgb = util_format_is_srgb(src_format), .samples = tu_msaa_samples(samples), .samples_average = !util_format_is_pure_integer(dst_format) && diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 2968cfb..d8e6f7d 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -167,8 +167,8 @@ tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer, tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE); if (flushes & TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE) { tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD( - .gfx_bindless = 0x1f, .cs_bindless = 0x1f, + .gfx_bindless = 0x1f, )); } if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES) @@ -205,9 +205,9 @@ rb_ccu_cntl(uint32_t color_offset, bool gmem) uint32_t color_offset_hi = color_offset >> 21; color_offset &= 0x1fffff; return A6XX_RB_CCU_CNTL( - .color_offset = color_offset, .color_offset_hi = color_offset_hi, .gmem = gmem, + .color_offset = color_offset, ); } @@ -941,12 +941,12 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, - .gfx_shared_const = true, + .gfx_ibo = true, .cs_shared_const = true, - .gfx_bindless = 0x1f, - .cs_bindless = 0x1f)); + .gfx_shared_const = true, + .cs_bindless = 0x1f, + .gfx_bindless = 0x1f,)); tu_cs_emit_wfi(cs); @@ -5661,10 +5661,14 @@ tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd, [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0], [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1], [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2], + [IR3_DP_WORK_DIM] = 0, [IR3_DP_BASE_GROUP_X] = info->offsets[0], [IR3_DP_BASE_GROUP_Y] = info->offsets[1], [IR3_DP_BASE_GROUP_Z] = info->offsets[2], [IR3_DP_CS_SUBGROUP_SIZE] = subgroup_size, + [IR3_DP_LOCAL_GROUP_SIZE_X] = 0, + [IR3_DP_LOCAL_GROUP_SIZE_Y] = 0, + [IR3_DP_LOCAL_GROUP_SIZE_Z] = 0, [IR3_DP_SUBGROUP_ID_SHIFT] = subgroup_shift, }; diff --git a/src/freedreno/vulkan/tu_descriptor_set.c b/src/freedreno/vulkan/tu_descriptor_set.c index d6b5668..90ba0d3 100644 --- a/src/freedreno/vulkan/tu_descriptor_set.c +++ b/src/freedreno/vulkan/tu_descriptor_set.c @@ -1503,8 +1503,8 @@ tu_CreateDescriptorUpdateTemplate( templ->entry[j++] = (struct tu_descriptor_update_template_entry) { .descriptor_type = entry->descriptorType, .descriptor_count = count, - .src_offset = src_offset, .dst_offset = dst_offset, + .src_offset = src_offset, }; remaining -= count; src_offset += count; @@ -1532,11 +1532,11 @@ tu_CreateDescriptorUpdateTemplate( templ->entry[j++] = (struct tu_descriptor_update_template_entry) { .descriptor_type = entry->descriptorType, .descriptor_count = entry->descriptorCount, - .src_offset = entry->offset, - .src_stride = entry->stride, .dst_offset = dst_offset, .dst_stride = dst_stride, .has_sampler = !binding_layout->immutable_samplers_offset, + .src_offset = entry->offset, + .src_stride = entry->stride, .immutable_samplers = immutable_samplers, }; } diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c index 442a0bd..2dda3c5 100644 --- a/src/freedreno/vulkan/tu_device.c +++ b/src/freedreno/vulkan/tu_device.c @@ -85,15 +85,18 @@ tu_EnumerateInstanceVersion(uint32_t *pApiVersion) static const struct vk_instance_extension_table tu_instance_extensions_supported = { .KHR_device_group_creation = true, +#ifdef VK_USE_PLATFORM_DISPLAY_KHR + .KHR_display = true, +#endif .KHR_external_fence_capabilities = true, .KHR_external_memory_capabilities = true, .KHR_external_semaphore_capabilities = true, +#ifdef VK_USE_PLATFORM_DISPLAY_KHR + .KHR_get_display_properties2 = true, +#endif .KHR_get_physical_device_properties2 = true, - .KHR_surface = TU_HAS_SURFACE, .KHR_get_surface_capabilities2 = TU_HAS_SURFACE, - .EXT_swapchain_colorspace = TU_HAS_SURFACE, - .EXT_debug_report = true, - .EXT_debug_utils = true, + .KHR_surface = TU_HAS_SURFACE, #ifdef VK_USE_PLATFORM_WAYLAND_KHR .KHR_wayland_surface = true, #endif @@ -103,16 +106,19 @@ static const struct vk_instance_extension_table tu_instance_extensions_supported #ifdef VK_USE_PLATFORM_XLIB_KHR .KHR_xlib_surface = true, #endif +#ifdef VK_USE_PLATFORM_DISPLAY_KHR + .EXT_acquire_drm_display = true, +#endif #ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT .EXT_acquire_xlib_display = true, #endif + .EXT_debug_report = true, + .EXT_debug_utils = true, #ifdef VK_USE_PLATFORM_DISPLAY_KHR - .KHR_display = true, - .KHR_get_display_properties2 = true, .EXT_direct_mode_display = true, .EXT_display_surface_counter = true, - .EXT_acquire_drm_display = true, #endif + .EXT_swapchain_colorspace = TU_HAS_SURFACE, }; static bool @@ -128,6 +134,7 @@ get_device_extensions(const struct tu_physical_device *device, *ext = (struct vk_device_extension_table) { .KHR_16bit_storage = device->info->a6xx.storage_16bit, .KHR_bind_memory2 = true, + .KHR_buffer_device_address = true, .KHR_copy_commands2 = true, .KHR_create_renderpass2 = true, .KHR_dedicated_allocation = true, @@ -135,6 +142,8 @@ get_device_extensions(const struct tu_physical_device *device, .KHR_descriptor_update_template = true, .KHR_device_group = true, .KHR_draw_indirect_count = true, + .KHR_driver_properties = true, + .KHR_dynamic_rendering = true, .KHR_external_fence = true, .KHR_external_fence_fd = true, .KHR_external_memory = true, @@ -144,9 +153,9 @@ get_device_extensions(const struct tu_physical_device *device, .KHR_format_feature_flags2 = true, .KHR_get_memory_requirements2 = true, .KHR_global_priority = true, + .KHR_image_format_list = true, .KHR_imageless_framebuffer = true, .KHR_incremental_present = TU_HAS_SURFACE, - .KHR_image_format_list = true, .KHR_maintenance1 = true, .KHR_maintenance2 = true, .KHR_maintenance3 = true, @@ -154,30 +163,8 @@ get_device_extensions(const struct tu_physical_device *device, .KHR_multiview = true, .KHR_performance_query = TU_DEBUG(PERFC), .KHR_pipeline_executable_properties = true, - .KHR_push_descriptor = true, - .KHR_relaxed_block_layout = true, - .KHR_sampler_mirror_clamp_to_edge = true, - .KHR_sampler_ycbcr_conversion = true, - .KHR_shader_draw_parameters = true, - .KHR_shader_float_controls = true, - .KHR_shader_float16_int8 = true, - .KHR_shader_subgroup_extended_types = true, - .KHR_shader_terminate_invocation = true, - .KHR_spirv_1_4 = true, - .KHR_storage_buffer_storage_class = true, - .KHR_swapchain = TU_HAS_SURFACE, - .KHR_swapchain_mutable_format = TU_HAS_SURFACE, - .KHR_uniform_buffer_standard_layout = true, - .KHR_variable_pointers = true, - .KHR_vulkan_memory_model = true, - .KHR_driver_properties = true, - .KHR_separate_depth_stencil_layouts = true, - .KHR_buffer_device_address = true, - .KHR_shader_integer_dot_product = true, - .KHR_zero_initialize_workgroup_memory = true, - .KHR_shader_non_semantic_info = true, - .KHR_synchronization2 = true, - .KHR_dynamic_rendering = true, + .KHR_pipeline_library = true, + /* Hide these behind dri configs for now since we cannot implement it reliably on * all surfaces yet. There is no surface capability query for present wait/id, * but the feature is useful enough to hide behind an opt-in mechanism for now. @@ -193,75 +180,98 @@ get_device_extensions(const struct tu_physical_device *device, "vk_khr_present_wait") || wsi_common_vk_instance_supports_present_wait( &device->instance->vk)), + + .KHR_push_descriptor = true, + .KHR_relaxed_block_layout = true, + .KHR_sampler_mirror_clamp_to_edge = true, + .KHR_sampler_ycbcr_conversion = true, + .KHR_separate_depth_stencil_layouts = true, + .KHR_shader_draw_parameters = true, + .KHR_shader_float16_int8 = true, + .KHR_shader_float_controls = true, + .KHR_shader_integer_dot_product = true, + .KHR_shader_non_semantic_info = true, + .KHR_shader_subgroup_extended_types = true, + .KHR_shader_terminate_invocation = true, + .KHR_spirv_1_4 = true, + .KHR_storage_buffer_storage_class = true, + .KHR_swapchain = TU_HAS_SURFACE, + .KHR_swapchain_mutable_format = TU_HAS_SURFACE, + .KHR_synchronization2 = true, .KHR_timeline_semaphore = true, -#ifdef VK_USE_PLATFORM_DISPLAY_KHR - .EXT_display_control = true, -#endif - .EXT_external_memory_dma_buf = true, - .EXT_image_drm_format_modifier = true, - .EXT_sample_locations = device->info->a6xx.has_sample_locations, - .EXT_sampler_filter_minmax = true, - .EXT_transform_feedback = true, + .KHR_uniform_buffer_standard_layout = true, + .KHR_variable_pointers = true, + .KHR_vulkan_memory_model = true, + .KHR_zero_initialize_workgroup_memory = true, + .EXT_4444_formats = true, + .EXT_attachment_feedback_loop_layout = true, .EXT_border_color_swizzle = true, + .EXT_color_write_enable = true, .EXT_conditional_rendering = true, .EXT_custom_border_color = true, .EXT_depth_clip_control = true, .EXT_depth_clip_enable = true, + .EXT_descriptor_buffer = true, .EXT_descriptor_indexing = true, +#ifdef VK_USE_PLATFORM_DISPLAY_KHR + .EXT_display_control = true, +#endif .EXT_extended_dynamic_state = true, .EXT_extended_dynamic_state2 = true, .EXT_extended_dynamic_state3 = true, + .EXT_external_memory_dma_buf = true, .EXT_filter_cubic = device->info->a6xx.has_tex_filter_cubic, .EXT_global_priority = true, .EXT_global_priority_query = true, + .EXT_graphics_pipeline_library = true, .EXT_host_query_reset = true, + .EXT_image_2d_view_of_3d = true, + .EXT_image_drm_format_modifier = true, + .EXT_image_robustness = true, + .EXT_image_view_min_lod = true, .EXT_index_type_uint8 = true, + .EXT_inline_uniform_block = true, + .EXT_line_rasterization = true, + .EXT_load_store_op_none = true, .EXT_memory_budget = true, + .EXT_multi_draw = true, + .EXT_mutable_descriptor_type = true, + .EXT_non_seamless_cube_map = true, + .EXT_physical_device_drm = !is_kgsl(device->instance), + .EXT_pipeline_creation_cache_control = true, + .EXT_pipeline_creation_feedback = true, + .EXT_post_depth_coverage = true, .EXT_primitive_topology_list_restart = true, + .EXT_primitives_generated_query = true, .EXT_private_data = true, + .EXT_provoking_vertex = true, .EXT_queue_family_foreign = true, + .EXT_rasterization_order_attachment_access = true, .EXT_robustness2 = true, + .EXT_sample_locations = device->info->a6xx.has_sample_locations, + .EXT_sampler_filter_minmax = true, .EXT_scalar_block_layout = true, .EXT_separate_stencil_usage = true, .EXT_shader_demote_to_helper_invocation = true, + .EXT_shader_module_identifier = true, .EXT_shader_stencil_export = true, .EXT_shader_viewport_index_layer = true, - .EXT_shader_module_identifier = true, + .EXT_subgroup_size_control = true, .EXT_texel_buffer_alignment = true, + .EXT_tooling_info = true, + .EXT_transform_feedback = true, .EXT_vertex_attribute_divisor = true, - .EXT_provoking_vertex = true, - .EXT_line_rasterization = true, - .EXT_subgroup_size_control = true, - .EXT_image_robustness = true, - .EXT_primitives_generated_query = true, - .EXT_image_view_min_lod = true, - .EXT_pipeline_creation_feedback = true, - .EXT_pipeline_creation_cache_control = true, .EXT_vertex_input_dynamic_state = true, - .EXT_attachment_feedback_loop_layout = true, - .EXT_rasterization_order_attachment_access = true, - .EXT_multi_draw = true, - .EXT_physical_device_drm = !is_kgsl(device->instance), + /* For Graphics Flight Recorder (GFR) */ .AMD_buffer_marker = true, - .ARM_rasterization_order_attachment_access = true, #ifdef ANDROID .ANDROID_native_buffer = true, #endif + .ARM_rasterization_order_attachment_access = true, .IMG_filter_cubic = device->info->a6xx.has_tex_filter_cubic, .VALVE_mutable_descriptor_type = true, - .EXT_image_2d_view_of_3d = true, - .EXT_color_write_enable = true, - .EXT_load_store_op_none = true, - .EXT_non_seamless_cube_map = true, - .EXT_tooling_info = true, - .EXT_inline_uniform_block = true, - .EXT_mutable_descriptor_type = true, - .KHR_pipeline_library = true, - .EXT_graphics_pipeline_library = true, - .EXT_post_depth_coverage = true, - .EXT_descriptor_buffer = true, }; } @@ -639,12 +649,12 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, .shaderImageGatherExtended = true, .shaderStorageImageExtendedFormats = true, .shaderStorageImageMultisample = false, + .shaderStorageImageReadWithoutFormat = true, + .shaderStorageImageWriteWithoutFormat = true, .shaderUniformBufferArrayDynamicIndexing = true, .shaderSampledImageArrayDynamicIndexing = true, .shaderStorageBufferArrayDynamicIndexing = true, .shaderStorageImageArrayDynamicIndexing = true, - .shaderStorageImageReadWithoutFormat = true, - .shaderStorageImageWriteWithoutFormat = true, .shaderClipDistance = true, .shaderCullDistance = true, .shaderFloat64 = false, @@ -2737,9 +2747,9 @@ tu_get_buffer_memory_requirements(uint64_t size, VkMemoryRequirements2 *pMemoryRequirements) { pMemoryRequirements->memoryRequirements = (VkMemoryRequirements) { - .memoryTypeBits = 1, - .alignment = 64, .size = MAX2(align64(size, 64), size), + .alignment = 64, + .memoryTypeBits = 1, }; vk_foreach_struct(ext, pMemoryRequirements->pNext) { diff --git a/src/freedreno/vulkan/tu_dynamic_rendering.c b/src/freedreno/vulkan/tu_dynamic_rendering.c index fcc45f4..49321a8 100644 --- a/src/freedreno/vulkan/tu_dynamic_rendering.c +++ b/src/freedreno/vulkan/tu_dynamic_rendering.c @@ -94,8 +94,8 @@ tu_init_dynamic_rendering(struct tu_device *dev) return vk_common_CreateCommandPool(tu_device_to_handle(dev), &(VkCommandPoolCreateInfo) { + .sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO, .pNext = NULL, - .sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO, .flags = 0, .queueFamilyIndex = 0, }, &dev->vk.alloc, diff --git a/src/freedreno/vulkan/tu_image.c b/src/freedreno/vulkan/tu_image.c index 7e250cd..3f9e312 100644 --- a/src/freedreno/vulkan/tu_image.c +++ b/src/freedreno/vulkan/tu_image.c @@ -756,9 +756,9 @@ tu_get_image_memory_requirements(struct tu_image *image, VkMemoryRequirements2 *pMemoryRequirements) { pMemoryRequirements->memoryRequirements = (VkMemoryRequirements) { - .memoryTypeBits = 1, + .size = image->total_size, .alignment = image->layout[0].base_align, - .size = image->total_size + .memoryTypeBits = 1, }; vk_foreach_struct(ext, pMemoryRequirements->pNext) { diff --git a/src/freedreno/vulkan/tu_knl_drm_msm.c b/src/freedreno/vulkan/tu_knl_drm_msm.c index 07a998b..0783db1 100644 --- a/src/freedreno/vulkan/tu_knl_drm_msm.c +++ b/src/freedreno/vulkan/tu_knl_drm_msm.c @@ -341,9 +341,9 @@ tu_bo_init(struct tu_device *dev, .gem_handle = gem_handle, .size = size, .iova = iova, + .name = name, .refcnt = 1, .bo_list_idx = idx, - .name = name, }; mtx_unlock(&dev->bo_mutex); @@ -968,11 +968,11 @@ tu_queue_submit_locked(struct tu_queue *queue, struct tu_queue_submit *submit) struct drm_msm_gem_submit req = { .flags = flags, - .queueid = queue->msm_queue_id, - .bos = (uint64_t)(uintptr_t) queue->device->bo_list, .nr_bos = submit->entry_count ? queue->device->bo_count : 0, - .cmds = (uint64_t)(uintptr_t)submit->cmds, .nr_cmds = submit->entry_count, + .bos = (uint64_t)(uintptr_t) queue->device->bo_list, + .cmds = (uint64_t)(uintptr_t)submit->cmds, + .queueid = queue->msm_queue_id, .in_syncobjs = (uint64_t)(uintptr_t)submit->in_syncobjs, .out_syncobjs = (uint64_t)(uintptr_t)submit->out_syncobjs, .nr_in_syncobjs = submit->nr_in_syncobjs, diff --git a/src/freedreno/vulkan/tu_knl_kgsl.c b/src/freedreno/vulkan/tu_knl_kgsl.c index 3c04b1e..8a82d00 100644 --- a/src/freedreno/vulkan/tu_knl_kgsl.c +++ b/src/freedreno/vulkan/tu_knl_kgsl.c @@ -100,8 +100,8 @@ kgsl_bo_init(struct tu_device *dev, .gem_handle = req.id, .size = req.mmapsize, .iova = req.gpuaddr, - .refcnt = 1, .name = tu_debug_bos_add(dev, req.mmapsize, name), + .refcnt = 1, }; *out_bo = bo; @@ -149,8 +149,8 @@ kgsl_bo_init_dmabuf(struct tu_device *dev, .gem_handle = req.id, .size = info_req.size, .iova = info_req.gpuaddr, - .refcnt = 1, .name = tu_debug_bos_add(dev, info_req.size, "dmabuf"), + .refcnt = 1, }; *out_bo = bo; @@ -277,8 +277,8 @@ timestamp_to_fd(struct tu_queue *queue, uint32_t timestamp) int fd; struct kgsl_timestamp_event event = { .type = KGSL_TIMESTAMP_EVENT_FENCE, - .context_id = queue->msm_queue_id, .timestamp = timestamp, + .context_id = queue->msm_queue_id, .priv = &fd, .len = sizeof(fd), }; @@ -1012,13 +1012,13 @@ kgsl_queue_submit(struct tu_queue *queue, struct vk_queue_submit *vk_submit) struct kgsl_gpu_command req = { .flags = KGSL_CMDBATCH_SUBMIT_IB_LIST, - .context_id = queue->msm_queue_id, .cmdlist = (uintptr_t) cmds, - .numcmds = entry_idx, .cmdsize = sizeof(struct kgsl_command_object), + .numcmds = entry_idx, .synclist = (uintptr_t) &sync, .syncsize = sizeof(sync), .numsyncs = has_sync != 0 ? 1 : 0, + .context_id = queue->msm_queue_id, }; int ret = safe_ioctl(queue->device->physical_device->local_fd, diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index cdd9ed5..ab02e5b 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -470,54 +470,54 @@ tu6_emit_xs(struct tu_cs *cs, switch (stage) { case MESA_SHADER_VERTEX: tu_cs_emit_regs(cs, A6XX_SP_VS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), .mergedregs = xs->mergedregs, )); break; case MESA_SHADER_TESS_CTRL: tu_cs_emit_regs(cs, A6XX_SP_HS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), )); break; case MESA_SHADER_TESS_EVAL: tu_cs_emit_regs(cs, A6XX_SP_DS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), )); break; case MESA_SHADER_GEOMETRY: tu_cs_emit_regs(cs, A6XX_SP_GS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), )); break; case MESA_SHADER_FRAGMENT: tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), - .mergedregs = xs->mergedregs, .threadsize = thrsz, - .pixlodenable = xs->need_pixlod, - .diff_fine = xs->need_fine_derivatives, .varying = xs->total_in != 0, + .diff_fine = xs->need_fine_derivatives, /* unknown bit, seems unnecessary */ .unk24 = true, + .pixlodenable = xs->need_pixlod, + .mergedregs = xs->mergedregs, )); break; case MESA_SHADER_COMPUTE: tu_cs_emit_regs(cs, A6XX_SP_CS_CTRL_REG0( - .fullregfootprint = xs->info.max_reg + 1, .halfregfootprint = xs->info.max_half_reg + 1, + .fullregfootprint = xs->info.max_reg + 1, .branchstack = ir3_shader_branchstack_hw(xs), - .mergedregs = xs->mergedregs, .threadsize = thrsz, + .mergedregs = xs->mergedregs, )); break; default: @@ -2357,21 +2357,22 @@ tu6_emit_blend_control(struct tu_pipeline *pipeline, msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff) : 0xffff; - pipeline->blend.sp_blend_cntl = - A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask, - .dual_color_in_enable = dual_src_blend, - .alpha_to_coverage = msaa_info->alphaToCoverageEnable, - .unk8 = true).value & pipeline->blend.sp_blend_cntl_mask; + A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask, + .unk8 = true, + .dual_color_in_enable = dual_src_blend, + .alpha_to_coverage = + msaa_info->alphaToCoverageEnable, ).value & + pipeline->blend.sp_blend_cntl_mask; /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */ pipeline->blend.rb_blend_cntl = A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask, .independent_blend = true, - .sample_mask = sample_mask, .dual_color_in_enable = dual_src_blend, .alpha_to_coverage = msaa_info->alphaToCoverageEnable, - .alpha_to_one = msaa_info->alphaToOneEnable).value & + .alpha_to_one = msaa_info->alphaToOneEnable, + .sample_mask = sample_mask,).value & pipeline->blend.rb_blend_cntl_mask; } @@ -2677,11 +2678,11 @@ tu_append_executable(struct tu_pipeline *pipeline, struct ir3_shader_variant *va { struct tu_pipeline_executable exe = { .stage = variant->type, + .stats = variant->info, + .is_binning = variant->binning_pass, .nir_from_spirv = nir_from_spirv, .nir_final = ralloc_strdup(pipeline->executables_mem_ctx, variant->disasm_info.nir), .disasm = ralloc_strdup(pipeline->executables_mem_ctx, variant->disasm_info.disasm), - .stats = variant->info, - .is_binning = variant->binning_pass, }; util_dynarray_append(&pipeline->executables, struct tu_pipeline_executable, exe); @@ -4131,8 +4132,8 @@ tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder, .sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_BINDING_DESCRIPTION_2_EXT, .pNext = NULL, .binding = binding->binding, - .inputRate = binding->inputRate, .stride = binding->stride, + .inputRate = binding->inputRate, .divisor = 1, }; @@ -4156,10 +4157,10 @@ tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder, attrs[i] = (VkVertexInputAttributeDescription2EXT) { .sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT, .pNext = NULL, - .binding = attr->binding, .location = attr->location, - .offset = attr->offset, + .binding = attr->binding, .format = attr->format, + .offset = attr->offset, }; } @@ -4907,8 +4908,8 @@ tu_pipeline_builder_init_graphics( .device = dev, .mem_ctx = ralloc_context(NULL), .cache = cache, - .create_info = create_info, .alloc = alloc, + .create_info = create_info, }; const VkGraphicsPipelineLibraryCreateInfoEXT *gpl_info = diff --git a/src/freedreno/vulkan/tu_query.c b/src/freedreno/vulkan/tu_query.c index a13f2d4..8c90d31 100644 --- a/src/freedreno/vulkan/tu_query.c +++ b/src/freedreno/vulkan/tu_query.c @@ -134,8 +134,8 @@ struct PACKED primitives_generated_query_slot { static const VkPerformanceCounterUnitKHR fd_perfcntr_type_to_vk_unit[] = { - [FD_PERFCNTR_TYPE_UINT] = VK_PERFORMANCE_COUNTER_UNIT_GENERIC_KHR, [FD_PERFCNTR_TYPE_UINT64] = VK_PERFORMANCE_COUNTER_UNIT_GENERIC_KHR, + [FD_PERFCNTR_TYPE_UINT] = VK_PERFORMANCE_COUNTER_UNIT_GENERIC_KHR, [FD_PERFCNTR_TYPE_FLOAT] = VK_PERFORMANCE_COUNTER_UNIT_GENERIC_KHR, [FD_PERFCNTR_TYPE_PERCENTAGE] = VK_PERFORMANCE_COUNTER_UNIT_PERCENTAGE_KHR, [FD_PERFCNTR_TYPE_BYTES] = VK_PERFORMANCE_COUNTER_UNIT_BYTES_KHR, @@ -155,8 +155,8 @@ fd_perfcntr_type_to_vk_unit[] = { */ static const VkPerformanceCounterStorageKHR fd_perfcntr_type_to_vk_storage[] = { - [FD_PERFCNTR_TYPE_UINT] = VK_PERFORMANCE_COUNTER_STORAGE_UINT32_KHR, [FD_PERFCNTR_TYPE_UINT64] = VK_PERFORMANCE_COUNTER_STORAGE_UINT64_KHR, + [FD_PERFCNTR_TYPE_UINT] = VK_PERFORMANCE_COUNTER_STORAGE_UINT32_KHR, [FD_PERFCNTR_TYPE_FLOAT] = VK_PERFORMANCE_COUNTER_STORAGE_FLOAT32_KHR, [FD_PERFCNTR_TYPE_PERCENTAGE] = VK_PERFORMANCE_COUNTER_STORAGE_FLOAT32_KHR, [FD_PERFCNTR_TYPE_BYTES] = VK_PERFORMANCE_COUNTER_STORAGE_UINT64_KHR, diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c index 1f414f8..46a94d5 100644 --- a/src/freedreno/vulkan/tu_shader.c +++ b/src/freedreno/vulkan/tu_shader.c @@ -26,58 +26,59 @@ tu_spirv_to_nir(struct tu_device *dev, { /* TODO these are made-up */ const struct spirv_to_nir_options spirv_options = { - .ubo_addr_format = nir_address_format_vec2_index_32bit_offset, - .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset, - - /* Accessed via stg/ldg */ - .phys_ssbo_addr_format = nir_address_format_64bit_global, - - /* Accessed via the const register file */ - .push_const_addr_format = nir_address_format_logical, - - /* Accessed via ldl/stl */ - .shared_addr_format = nir_address_format_32bit_offset, - - /* Accessed via stg/ldg (not used with Vulkan?) */ - .global_addr_format = nir_address_format_64bit_global, + /* ViewID is a sysval in geometry stages and an input in the FS */ + .view_index_is_input = stage == MESA_SHADER_FRAGMENT, /* Use 16-bit math for RelaxedPrecision ALU ops */ .mediump_16bit_alu = true, - /* ViewID is a sysval in geometry stages and an input in the FS */ - .view_index_is_input = stage == MESA_SHADER_FRAGMENT, .caps = { - .transform_feedback = true, - .tessellation = true, - .draw_parameters = true, - .image_read_without_format = true, - .image_write_without_format = true, - .variable_pointers = true, - .stencil_export = true, - .multiview = true, - .shader_viewport_index_layer = true, - .geometry_streams = true, - .device_group = true, - .descriptor_indexing = true, + .demote_to_helper_invocation = true, .descriptor_array_dynamic_indexing = true, .descriptor_array_non_uniform_indexing = true, - .runtime_descriptor_array = true, + .descriptor_indexing = true, + .device_group = true, + .draw_parameters = true, .float_controls = true, .float16 = true, + .geometry_streams = true, + .image_read_without_format = true, + .image_write_without_format = true, .int16 = true, + .multiview = true, + .physical_storage_buffer_address = true, + .post_depth_coverage = true, + .runtime_descriptor_array = true, + .shader_viewport_index_layer = true, + .stencil_export = true, .storage_16bit = dev->physical_device->info->a6xx.storage_16bit, - .demote_to_helper_invocation = true, - .vk_memory_model = true, - .vk_memory_model_device_scope = true, - .subgroup_basic = true, + .subgroup_arithmetic = true, .subgroup_ballot = true, - .subgroup_vote = true, + .subgroup_basic = true, .subgroup_quad = true, .subgroup_shuffle = true, - .subgroup_arithmetic = true, - .physical_storage_buffer_address = true, - .post_depth_coverage = true, + .subgroup_vote = true, + .tessellation = true, + .transform_feedback = true, + .variable_pointers = true, + .vk_memory_model_device_scope = true, + .vk_memory_model = true, }, + + .ubo_addr_format = nir_address_format_vec2_index_32bit_offset, + .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset, + + /* Accessed via stg/ldg */ + .phys_ssbo_addr_format = nir_address_format_64bit_global, + + /* Accessed via the const register file */ + .push_const_addr_format = nir_address_format_logical, + + /* Accessed via ldl/stl */ + .shared_addr_format = nir_address_format_32bit_offset, + + /* Accessed via stg/ldg (not used with Vulkan?) */ + .global_addr_format = nir_address_format_64bit_global, }; const nir_shader_compiler_options *nir_options = @@ -802,9 +803,9 @@ tu_lower_io(nir_shader *shader, struct tu_device *dev, const_state->ubos[const_state->num_inline_ubos++] = (struct tu_inline_ubo) { .base = set, .offset = binding->offset, + .push_address = push_address, .const_offset_vec4 = reserved_consts_vec4, .size_vec4 = size_vec4, - .push_address = push_address, }; reserved_consts_vec4 += align(size_vec4, dev->compiler->const_upload_unit); @@ -1016,9 +1017,9 @@ tu_shader_create(struct tu_device *dev, shader->ir3_shader = ir3_shader_from_nir(dev->compiler, nir, &(struct ir3_shader_options) { .reserved_user_consts = shader->reserved_user_consts_vec4, - .shared_consts_enable = shared_consts_enable, .api_wavesize = key->api_wavesize, .real_wavesize = key->real_wavesize, + .shared_consts_enable = shared_consts_enable, }, &so_info); return shader; -- 2.7.4