From dfa41387155daed35cc6b294b2390641aa887a1d Mon Sep 17 00:00:00 2001
From: =?utf8?q?Vincent=20Stehl=C3=A9?= <v-stehle@ti.com>
Date: Mon, 4 Mar 2013 20:04:43 +0000
Subject: [PATCH] ARM: cache: declare set_section_dcache
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

We declare the set_section_dcache function globally in the cache header, for
later use by e.g. machine specific code.

Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com>
Cc: Tom Rini <trini <at> ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 arch/arm/include/asm/cache.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index eef6a5a..416d2c8 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void)
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
+void set_section_dcache(int section, enum dcache_option option);
 
 /*
  * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
-- 
2.7.4