From df08a6fc0d5d7dd579dd0902893a433765d9f4c5 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 26 May 2022 13:29:46 +1200 Subject: [PATCH] dt-bindings: gpio: gpio-mvebu: document offset and marvell,pwm-offset MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The offset and marvell,pwm-offset properties weren't in the old binding. Add them based on the existing usage in the driver and board DTS when the marvell,armada-8k-gpio compatible is used. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski Acked-by: Uwe Kleine-König Acked-by: Thierry Reding Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml index 459ec358..f1bd1e6 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml @@ -45,6 +45,10 @@ properties: - const: pwm minItems: 1 + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the gpio registers (in bytes) + interrupts: description: | The list of interrupts that are used for all the pins managed by this @@ -68,6 +72,10 @@ properties: "#gpio-cells": const: 2 + marvell,pwm-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the pwm registers (in bytes) + "#pwm-cells": description: The first cell is the GPIO line number. The second cell is the period -- 2.7.4