From dec57795efc4585d5bbca913af6683c5cce2a647 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 17 Jul 2023 15:11:22 +0200 Subject: [PATCH] clk: renesas: r8a77965: Add 3DGE and ZG support The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/1767d01cfffd7490861f2cf6ad6c0df100916907.1689599217.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 78f6e53..e455ec0 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -125,6 +126,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A77965_CLK_ZG), DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6), DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2), -- 2.7.4