From dea26950a020bfb65aeedcc5d2afaa574adbedbb Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 12 Sep 2016 19:50:08 +0000
Subject: [PATCH] [InstCombine] add test for PR30327

llvm-svn: 281248
---
 llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
index 735b07c..d252ad0 100644
--- a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
+++ b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
+
 ; rdar://11748024
 
 define i32 @a(i1 zeroext %x, i1 zeroext %y) {
@@ -17,3 +18,16 @@ define i32 @a(i1 zeroext %x, i1 zeroext %y) {
   ret i32 %add
 }
 
+define i32 @PR30273(i1 %a, i1 %b) {
+; CHECK-LABEL: @PR30273(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext i1 %a to i32
+; CHECK-NEXT:    [[SEL1:%.*]] = select i1 %a, i32 2, i32 1
+; CHECK-NEXT:    [[SEL2:%.*]] = select i1 %b, i32 [[SEL1]], i32 [[ZEXT]]
+; CHECK-NEXT:    ret i32 [[SEL2]]
+;
+  %zext = zext i1 %a to i32
+  %sel1 = select i1 %a, i32 2, i32 1
+  %sel2 = select i1 %b, i32 %sel1, i32 %zext
+  ret i32 %sel2
+}
+
-- 
2.7.4