From de5f196530b508df3bc8c035ae1db87b56437d88 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Sat, 7 Apr 2018 05:36:44 +0000 Subject: [PATCH] Revert "ARM: Do not spill CSR to stack on entry to noreturn functions" Breaks ubsan test TestCases/Misc/missing_return.cpp on ARM This reverts commit r329287 llvm-svn: 329486 --- llvm/include/llvm/CodeGen/TargetFrameLowering.h | 4 -- llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 18 -------- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 11 ----- llvm/lib/Target/ARM/ARMFrameLowering.h | 2 - llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll | 4 +- llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll | 2 +- llvm/test/CodeGen/ARM/noreturn-csr-skip.mir | 51 ---------------------- llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll | 2 +- llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll | 2 +- .../CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | 10 ++--- llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 2 +- 11 files changed, 11 insertions(+), 97 deletions(-) delete mode 100644 llvm/test/CodeGen/ARM/noreturn-csr-skip.mir diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h index 637b73c..61f1cf0 100644 --- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -158,10 +158,6 @@ public: return false; } - /// Returns true if the target can safely skip saving callee-saved registers - /// for noreturn nounwind functions. - virtual bool enableCalleeSaveSkip(const MachineFunction &MF) const; - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. virtual void emitPrologue(MachineFunction &MF, diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 76c5425..79fafa5 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -36,12 +36,6 @@ bool TargetFrameLowering::noFramePointerElim(const MachineFunction &MF) const { return Attr.getValueAsString() == "true"; } -bool TargetFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const { - assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) && - MF.getFunction().hasFnAttribute(Attribute::NoUnwind)); - return false; -} - /// Returns the displacement from the frame register to the stack /// frame of the specified index, along with the frame register used /// (in output arg FrameReg). This is the default implementation which @@ -91,18 +85,6 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF, if (MF.getFunction().hasFnAttribute(Attribute::Naked)) return; - // Noreturn+nounwind functions never restore CSR, so no saves are needed. - // Purely noreturn functions may still return through throws, so those must - // save CSR for caller exception handlers. - // - // If the function uses longjmp to break out of its current path of - // execution we do not need the CSR spills either: setjmp stores all CSRs - // it was called with into the jmp_buf, which longjmp then restores. - if (MF.getFunction().hasFnAttribute(Attribute::NoReturn) && - MF.getFunction().hasFnAttribute(Attribute::NoUnwind) && - enableCalleeSaveSkip(MF)) - return; - // Functions which call __builtin_unwind_init get all their registers saved. bool CallsUnwindInit = MF.callsUnwindInit(); const MachineRegisterInfo &MRI = MF.getRegInfo(); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index f9d2b60..5da1e76 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -87,17 +87,6 @@ bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const { MF.getSubtarget().useFastISel(); } -/// Returns true if the target can safely skip saving callee-saved registers -/// for noreturn nounwind functions. -bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const { - assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) && - MF.getFunction().hasFnAttribute(Attribute::NoUnwind)); - - // Frame pointer and link register are not treated as normal CSR, thus we - // can always skip CSR saves for nonreturning functions. - return true; -} - /// hasFP - Return true if the specified function should have a dedicated frame /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h index e994cab..1f18e2b 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.h +++ b/llvm/lib/Target/ARM/ARMFrameLowering.h @@ -44,8 +44,6 @@ public: bool noFramePointerElim(const MachineFunction &MF) const override; - bool enableCalleeSaveSkip(const MachineFunction &MF) const override; - bool hasFP(const MachineFunction &MF) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override; diff --git a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll index 7ae739e..0253229 100644 --- a/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll +++ b/llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll @@ -281,7 +281,7 @@ declare void @somethingElse(...) ; Shift second argument by one and store into returned register. ; ENABLE: lsl w0, w1, #1 ; ENABLE: ret -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { entry: %tobool = icmp eq i32 %cond, 0 br i1 %tobool, label %if.else, label %if.then @@ -355,7 +355,7 @@ entry: ; CHECK-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -define i32 @variadicFunc(i32 %cond, i32 %count, ...) nounwind { +define i32 @variadicFunc(i32 %cond, i32 %count, ...) #0 { entry: %ap = alloca i8*, align 8 %tobool = icmp eq i32 %cond, 0 diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll index c943f60c5..1985ff9 100644 --- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll +++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -327,7 +327,7 @@ declare void @somethingElse(...) ; DISABLE-NEXT: pop {r4, r7, pc} ; ; ENABLE-NEXT: bx lr -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" #0 { entry: %tobool = icmp eq i32 %cond, 0 br i1 %tobool, label %if.else, label %if.then diff --git a/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir b/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir deleted file mode 100644 index c3b9718..0000000 --- a/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir +++ /dev/null @@ -1,51 +0,0 @@ -# RUN: llc -mtriple thumbv7m-none-eabi -run-pass prologepilog %s -o - | FileCheck %s - ---- | - define void @throw() noreturn { unreachable } - - define void @ret() nounwind { ret void } - - define void @noret() noreturn nounwind { - start: - %p = alloca i32 - store i32 42, i32* %p - unreachable - } -... ---- -# This function may return by exception. Check that $r4 is saved and restored. -# CHECK-LABEL: name: throw -# CHECK: killed $r4 -# CHECK: def $r4 -name: throw -body: | - bb.0: - $r4 = IMPLICIT_DEF - tBX_RET 14, $noreg ---- ---- -# This function may return. Check that $r4 is saved and restored. -# CHECK-LABEL: name: ret -# CHECK: killed $r4 -# CHECK: def $r4 -name: ret -body: | - bb.0: - $r4 = IMPLICIT_DEF - tBX_RET 14, $noreg ---- ---- -# This function does not return. We need not save any CSR, but -# other stack adjustments in the prologue are still necessary. -# CHECK-LABEL: name: noret -# CHECK-NOT: killed $r4 -# CHECK-NOT: def $r4 -# CHECK: $sp = frame-setup -name: noret -stack: - - { id: 0, name: p, offset: 0, size: 4, alignment: 4, local-offset: -4 } -body: | - bb.0: - $r4 = IMPLICIT_DEF - tBX_RET 14, $noreg ---- diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll index 6886b4e..2bf4b07 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll @@ -328,7 +328,7 @@ declare void @somethingElse(...) ; Shift second argument by one and store into returned register. ; ENABLE: slwi 3, 4, 1 ; ENABLE-NEXT: blr -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { entry: %tobool = icmp eq i32 %cond, 0 br i1 %tobool, label %if.else, label %if.then diff --git a/llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll b/llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll index 5d93f30..4716262 100644 --- a/llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll +++ b/llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll @@ -374,7 +374,7 @@ declare void @somethingElse(...) ; ; ENABLE-V5T-NEXT: {{LBB[0-9_]+}}: @ %if.end ; ENABLE-NEXT: bx lr -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { entry: %tobool = icmp eq i32 %cond, 0 br i1 %tobool, label %if.else, label %if.then diff --git a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll index 9d3e18e..c3b12ed 100644 --- a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll +++ b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll @@ -17,10 +17,10 @@ %tupl = type [9 x i32] -declare fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) nounwind -declare fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) nounwind +declare fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) noreturn nounwind +declare fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind -define fastcc void @l186(%tupl* %r1) nounwind { +define fastcc void @l186(%tupl* %r1) noreturn nounwind { entry: %ptr1 = getelementptr %tupl, %tupl* %r1, i32 0, i32 0 %r2 = load i32, i32* %ptr1 @@ -44,10 +44,10 @@ entry: br i1 %cond, label %true, label %false true: - tail call fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) nounwind + tail call fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) noreturn nounwind ret void false: - tail call fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) nounwind + tail call fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind ret void } diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll index cc77efa..65a5c78 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -314,7 +314,7 @@ if.end: ; preds = %if.else, %for.end ; ENABLE: addl %esi, %esi ; ENABLE-NEXT: movl %esi, %eax ; ENABLE-NEXT: retq -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { entry: %tobool = icmp eq i32 %cond, 0 br i1 %tobool, label %if.else, label %if.then -- 2.7.4