From dde7ac7f3fa48919e735c830787ea55cc39583c8 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 19 Apr 2021 15:50:14 -0700 Subject: [PATCH] intel: Rename vk_to_gen keyword to vk_to_intel export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965 grep -E "vk_to_gen" -rIl $SEARCH_PATH | xargs sed -ie "s/vk_to_gen/vk_to_intel/g" Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke Part-of: --- src/intel/vulkan/anv_genX.h | 10 +++--- src/intel/vulkan/anv_pipeline.c | 4 +-- src/intel/vulkan/genX_cmd_buffer.c | 4 +-- src/intel/vulkan/genX_pipeline.c | 62 +++++++++++++++++++------------------- src/intel/vulkan/genX_state.c | 30 +++++++++--------- src/intel/vulkan/gfx7_cmd_buffer.c | 28 ++++++++--------- src/intel/vulkan/gfx8_cmd_buffer.c | 46 ++++++++++++++-------------- 7 files changed, 92 insertions(+), 92 deletions(-) diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index e1e4412..18d7cbc 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -36,15 +36,15 @@ #error This file is included by means other than anv_private.h #endif -extern const uint32_t genX(vk_to_gen_cullmode)[]; +extern const uint32_t genX(vk_to_intel_cullmode)[]; -extern const uint32_t genX(vk_to_gen_front_face)[]; +extern const uint32_t genX(vk_to_intel_front_face)[]; -extern const uint32_t genX(vk_to_gen_primitive_type)[]; +extern const uint32_t genX(vk_to_intel_primitive_type)[]; -extern const uint32_t genX(vk_to_gen_compare_op)[]; +extern const uint32_t genX(vk_to_intel_compare_op)[]; -extern const uint32_t genX(vk_to_gen_stencil_op)[]; +extern const uint32_t genX(vk_to_intel_stencil_op)[]; void genX(init_physical_device_state)(struct anv_physical_device *device); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index a820691..a6f36fa 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -348,7 +348,7 @@ void anv_DestroyPipeline( vk_free2(&device->vk.alloc, pAllocator, pipeline); } -static const uint32_t vk_to_gen_primitive_type[] = { +static const uint32_t vk_to_intel_primitive_type[] = { [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST, [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST, [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP, @@ -2290,7 +2290,7 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline, if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints); else - pipeline->topology = vk_to_gen_primitive_type[ia_info->topology]; + pipeline->topology = vk_to_intel_primitive_type[ia_info->topology]; return VK_SUCCESS; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 73a731a..c885482 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3394,8 +3394,8 @@ cmd_buffer_emit_clip(struct anv_cmd_buffer *cmd_buffer) struct GENX(3DSTATE_CLIP) clip = { GENX(3DSTATE_CLIP_header), #if GFX_VER <= 7 - .FrontWinding = genX(vk_to_gen_front_face)[d->front_face], - .CullMode = genX(vk_to_gen_cullmode)[d->cull_mode], + .FrontWinding = genX(vk_to_intel_front_face)[d->front_face], + .CullMode = genX(vk_to_intel_cullmode)[d->cull_mode], #endif }; uint32_t dwords[GENX(3DSTATE_CLIP_length)]; diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index f3e0f23..20edb9d 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -558,20 +558,20 @@ gfx7_ms_rast_mode(struct anv_graphics_pipeline *pipeline, } #endif -const uint32_t genX(vk_to_gen_cullmode)[] = { +const uint32_t genX(vk_to_intel_cullmode)[] = { [VK_CULL_MODE_NONE] = CULLMODE_NONE, [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT, [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK, [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH }; -const uint32_t genX(vk_to_gen_fillmode)[] = { +const uint32_t genX(vk_to_intel_fillmode)[] = { [VK_POLYGON_MODE_FILL] = FILL_MODE_SOLID, [VK_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME, [VK_POLYGON_MODE_POINT] = FILL_MODE_POINT, }; -const uint32_t genX(vk_to_gen_front_face)[] = { +const uint32_t genX(vk_to_intel_front_face)[] = { [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1, [VK_FRONT_FACE_CLOCKWISE] = 0 }; @@ -695,13 +695,13 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, raster.FrontWinding = dynamic_states & ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE ? - 0 : genX(vk_to_gen_front_face)[rs_info->frontFace]; + 0 : genX(vk_to_intel_front_face)[rs_info->frontFace]; raster.CullMode = dynamic_states & ANV_CMD_DIRTY_DYNAMIC_CULL_MODE ? - 0 : genX(vk_to_gen_cullmode)[rs_info->cullMode]; + 0 : genX(vk_to_intel_cullmode)[rs_info->cullMode]; - raster.FrontFaceFillMode = genX(vk_to_gen_fillmode)[rs_info->polygonMode]; - raster.BackFaceFillMode = genX(vk_to_gen_fillmode)[rs_info->polygonMode]; + raster.FrontFaceFillMode = genX(vk_to_intel_fillmode)[rs_info->polygonMode]; + raster.BackFaceFillMode = genX(vk_to_intel_fillmode)[rs_info->polygonMode]; raster.ScissorRectangleEnable = true; #if GFX_VER >= 9 @@ -806,7 +806,7 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline, } } -static const uint32_t vk_to_gen_logic_op[] = { +static const uint32_t vk_to_intel_logic_op[] = { [VK_LOGIC_OP_COPY] = LOGICOP_COPY, [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR, [VK_LOGIC_OP_AND] = LOGICOP_AND, @@ -825,7 +825,7 @@ static const uint32_t vk_to_gen_logic_op[] = { [VK_LOGIC_OP_SET] = LOGICOP_SET, }; -static const uint32_t vk_to_gen_blend[] = { +static const uint32_t vk_to_intel_blend[] = { [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO, [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE, [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR, @@ -847,7 +847,7 @@ static const uint32_t vk_to_gen_blend[] = { [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA, }; -static const uint32_t vk_to_gen_blend_op[] = { +static const uint32_t vk_to_intel_blend_op[] = { [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD, [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT, [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT, @@ -855,7 +855,7 @@ static const uint32_t vk_to_gen_blend_op[] = { [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX, }; -const uint32_t genX(vk_to_gen_compare_op)[] = { +const uint32_t genX(vk_to_intel_compare_op)[] = { [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER, [VK_COMPARE_OP_LESS] = PREFILTEROPLESS, [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL, @@ -866,7 +866,7 @@ const uint32_t genX(vk_to_gen_compare_op)[] = { [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS, }; -const uint32_t genX(vk_to_gen_stencil_op)[] = { +const uint32_t genX(vk_to_intel_stencil_op)[] = { [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP, [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO, [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE, @@ -877,7 +877,7 @@ const uint32_t genX(vk_to_gen_stencil_op)[] = { [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR, }; -const uint32_t genX(vk_to_gen_primitive_type)[] = { +const uint32_t genX(vk_to_intel_primitive_type)[] = { [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST, [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST, [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP, @@ -1081,7 +1081,7 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, .DepthTestFunction = dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP ? - 0 : genX(vk_to_gen_compare_op)[info.depthCompareOp], + 0 : genX(vk_to_intel_compare_op)[info.depthCompareOp], .DoubleSidedStencilEnable = true, @@ -1089,14 +1089,14 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE ? 0 : info.stencilTestEnable, - .StencilFailOp = genX(vk_to_gen_stencil_op)[info.front.failOp], - .StencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[info.front.passOp], - .StencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[info.front.depthFailOp], - .StencilTestFunction = genX(vk_to_gen_compare_op)[info.front.compareOp], - .BackfaceStencilFailOp = genX(vk_to_gen_stencil_op)[info.back.failOp], - .BackfaceStencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[info.back.passOp], - .BackfaceStencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[info.back.depthFailOp], - .BackfaceStencilTestFunction = genX(vk_to_gen_compare_op)[info.back.compareOp], + .StencilFailOp = genX(vk_to_intel_stencil_op)[info.front.failOp], + .StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[info.front.passOp], + .StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[info.front.depthFailOp], + .StencilTestFunction = genX(vk_to_intel_compare_op)[info.front.compareOp], + .BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[info.back.failOp], + .BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[info.back.passOp], + .BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[info.back.depthFailOp], + .BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[info.back.compareOp], }; if (dynamic_stencil_op) { @@ -1191,7 +1191,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable, #endif .LogicOpEnable = info->logicOpEnable, - .LogicOpFunction = vk_to_gen_logic_op[info->logicOp], + .LogicOpFunction = vk_to_intel_logic_op[info->logicOp], /* Vulkan specification 1.2.168, VkLogicOp: * * "Logical operations are controlled by the logicOpEnable and @@ -1211,12 +1211,12 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, .ColorClampRange = COLORCLAMP_RTFORMAT, .PreBlendColorClampEnable = true, .PostBlendColorClampEnable = true, - .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor], - .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor], - .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp], - .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor], - .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor], - .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp], + .SourceBlendFactor = vk_to_intel_blend[a->srcColorBlendFactor], + .DestinationBlendFactor = vk_to_intel_blend[a->dstColorBlendFactor], + .ColorBlendFunction = vk_to_intel_blend_op[a->colorBlendOp], + .SourceAlphaBlendFactor = vk_to_intel_blend[a->srcAlphaBlendFactor], + .DestinationAlphaBlendFactor = vk_to_intel_blend[a->dstAlphaBlendFactor], + .AlphaBlendFunction = vk_to_intel_blend_op[a->alphaBlendOp], .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT), .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT), .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT), @@ -1377,8 +1377,8 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline, !(last->vue_map.slots_valid & VARYING_BIT_LAYER); #if GFX_VER == 7 - clip.FrontWinding = genX(vk_to_gen_front_face)[rs_info->frontFace]; - clip.CullMode = genX(vk_to_gen_cullmode)[rs_info->cullMode]; + clip.FrontWinding = genX(vk_to_intel_front_face)[rs_info->frontFace]; + clip.CullMode = genX(vk_to_intel_cullmode)[rs_info->cullMode]; clip.ViewportZClipTestEnable = pipeline->depth_clip_enable; clip.UserClipDistanceClipTestEnableBitmask = last->clip_distance_mask; clip.UserClipDistanceCullTestEnableBitmask = last->cull_distance_mask; diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 43284d1..fd91f9b 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -577,7 +577,7 @@ genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples, #endif static uint32_t -vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable) +vk_to_intel_tex_filter(VkFilter filter, bool anisotropyEnable) { switch (filter) { default: @@ -590,17 +590,17 @@ vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable) } static uint32_t -vk_to_gen_max_anisotropy(float ratio) +vk_to_intel_max_anisotropy(float ratio) { return (anv_clamp_f(ratio, 2, 16) - 2) / 2; } -static const uint32_t vk_to_gen_mipmap_mode[] = { +static const uint32_t vk_to_intel_mipmap_mode[] = { [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST, [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR }; -static const uint32_t vk_to_gen_tex_address[] = { +static const uint32_t vk_to_intel_tex_address[] = { [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP, [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR, [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP, @@ -619,7 +619,7 @@ static const uint32_t vk_to_gen_tex_address[] = { * So, these look a bit strange because there's both a negation * and swapping of the arguments involved. */ -static const uint32_t vk_to_gen_shadow_compare_op[] = { +static const uint32_t vk_to_intel_shadow_compare_op[] = { [VK_COMPARE_OP_NEVER] = PREFILTEROPALWAYS, [VK_COMPARE_OP_LESS] = PREFILTEROPLEQUAL, [VK_COMPARE_OP_EQUAL] = PREFILTEROPNOTEQUAL, @@ -631,7 +631,7 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = { }; #if GFX_VER >= 9 -static const uint32_t vk_to_gen_sampler_reduction_mode[] = { +static const uint32_t vk_to_intel_sampler_reduction_mode[] = { [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER, [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM, [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM, @@ -700,7 +700,7 @@ VkResult genX(CreateSampler)( VkSamplerReductionModeCreateInfo *sampler_reduction = (VkSamplerReductionModeCreateInfo *) ext; sampler_reduction_mode = - vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode]; + vk_to_intel_sampler_reduction_mode[sampler_reduction->reductionMode]; enable_sampler_reduction = true; break; } @@ -765,7 +765,7 @@ VkResult genX(CreateSampler)( const uint32_t mip_filter_mode = isl_format_is_planar_yuv ? - MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode]; + MIPFILTER_NONE : vk_to_intel_mipmap_mode[pCreateInfo->mipmapMode]; struct GENX(SAMPLER_STATE) sampler_state = { .SamplerDisable = false, @@ -781,8 +781,8 @@ VkResult genX(CreateSampler)( .BaseMipLevel = 0.0, #endif .MipModeFilter = mip_filter_mode, - .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable), - .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable), + .MagModeFilter = vk_to_intel_tex_filter(mag_filter, pCreateInfo->anisotropyEnable), + .MinModeFilter = vk_to_intel_tex_filter(min_filter, pCreateInfo->anisotropyEnable), .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996), .AnisotropicAlgorithm = pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY, @@ -792,7 +792,7 @@ VkResult genX(CreateSampler)( .ChromaKeyIndex = 0, .ChromaKeyMode = 0, .ShadowFunction = - vk_to_gen_shadow_compare_op[pCreateInfo->compareEnable ? + vk_to_intel_shadow_compare_op[pCreateInfo->compareEnable ? pCreateInfo->compareOp : VK_COMPARE_OP_NEVER], .CubeSurfaceControlMode = OVERRIDE, @@ -802,7 +802,7 @@ VkResult genX(CreateSampler)( .LODClampMagnificationMode = MIPNONE, #endif - .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy), + .MaximumAnisotropy = vk_to_intel_max_anisotropy(pCreateInfo->maxAnisotropy), .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, @@ -811,9 +811,9 @@ VkResult genX(CreateSampler)( .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, .TrilinearFilterQuality = 0, .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates, - .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU], - .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV], - .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW], + .TCXAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeU], + .TCYAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeV], + .TCZAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeW], #if GFX_VER >= 9 .ReductionType = sampler_reduction_mode, diff --git a/src/intel/vulkan/gfx7_cmd_buffer.c b/src/intel/vulkan/gfx7_cmd_buffer.c index e5ecfb6..559a484 100644 --- a/src/intel/vulkan/gfx7_cmd_buffer.c +++ b/src/intel/vulkan/gfx7_cmd_buffer.c @@ -125,7 +125,7 @@ gfx7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) } #endif -static uint32_t vk_to_gen_index_type(VkIndexType type) +static uint32_t vk_to_intel_index_type(VkIndexType type) { switch (type) { case VK_INDEX_TYPE_UINT8_EXT: @@ -166,7 +166,7 @@ void genX(CmdBindIndexBuffer)( if (GFX_VERx10 == 75) cmd_buffer->state.restart_index = restart_index_for_type(indexType); cmd_buffer->state.gfx.gfx7.index_buffer = buffer; - cmd_buffer->state.gfx.gfx7.index_type = vk_to_gen_index_type(indexType); + cmd_buffer->state.gfx.gfx7.index_type = vk_to_intel_index_type(indexType); cmd_buffer->state.gfx.gfx7.index_offset = offset; } @@ -220,8 +220,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .GlobalDepthOffsetConstant = d->depth_bias.bias, .GlobalDepthOffsetScale = d->depth_bias.slope, .GlobalDepthOffsetClamp = d->depth_bias.clamp, - .FrontWinding = genX(vk_to_gen_front_face)[d->front_face], - .CullMode = genX(vk_to_gen_cullmode)[d->cull_mode], + .FrontWinding = genX(vk_to_intel_front_face)[d->front_face], + .CullMode = genX(vk_to_intel_cullmode)[d->cull_mode], }; GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); @@ -282,16 +282,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .DepthTestEnable = d->depth_test_enable, .DepthBufferWriteEnable = d->depth_test_enable && d->depth_write_enable, - .DepthTestFunction = genX(vk_to_gen_compare_op)[d->depth_compare_op], + .DepthTestFunction = genX(vk_to_intel_compare_op)[d->depth_compare_op], .StencilTestEnable = d->stencil_test_enable, - .StencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.fail_op], - .StencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.pass_op], - .StencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.depth_fail_op], - .StencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.front.compare_op], - .BackfaceStencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.fail_op], - .BackfaceStencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.pass_op], - .BackfaceStencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.depth_fail_op], - .BackfaceStencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.back.compare_op], + .StencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.fail_op], + .StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.pass_op], + .StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.depth_fail_op], + .StencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.front.compare_op], + .BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.fail_op], + .BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.pass_op], + .BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.depth_fail_op], + .BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.back.compare_op], }; GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil); @@ -340,7 +340,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) topology = d->primitive_topology; else - topology = genX(vk_to_gen_primitive_type)[d->primitive_topology]; + topology = genX(vk_to_intel_primitive_type)[d->primitive_topology]; cmd_buffer->state.gfx.primitive_topology = topology; } diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c index 2631247..dede0e4 100644 --- a/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/src/intel/vulkan/gfx8_cmd_buffer.c @@ -449,8 +449,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .GlobalDepthOffsetConstant = d->depth_bias.bias, .GlobalDepthOffsetScale = d->depth_bias.slope, .GlobalDepthOffsetClamp = d->depth_bias.clamp, - .CullMode = genX(vk_to_gen_cullmode)[d->cull_mode], - .FrontWinding = genX(vk_to_gen_front_face)[d->front_face], + .CullMode = genX(vk_to_intel_cullmode)[d->cull_mode], + .FrontWinding = genX(vk_to_intel_front_face)[d->front_face], }; GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster); anv_batch_emit_merge(&cmd_buffer->batch, raster_dw, @@ -511,16 +511,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .DepthTestEnable = d->depth_test_enable, .DepthBufferWriteEnable = d->depth_test_enable && d->depth_write_enable, - .DepthTestFunction = genX(vk_to_gen_compare_op)[d->depth_compare_op], + .DepthTestFunction = genX(vk_to_intel_compare_op)[d->depth_compare_op], .StencilTestEnable = d->stencil_test_enable, - .StencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.fail_op], - .StencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.pass_op], - .StencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.depth_fail_op], - .StencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.front.compare_op], - .BackfaceStencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.fail_op], - .BackfaceStencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.pass_op], - .BackfaceStencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.depth_fail_op], - .BackfaceStencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.back.compare_op], + .StencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.fail_op], + .StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.pass_op], + .StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.depth_fail_op], + .StencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.front.compare_op], + .BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.fail_op], + .BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.pass_op], + .BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.depth_fail_op], + .BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.back.compare_op], }; GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw, &wm_depth_stencil); @@ -580,16 +580,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .DepthTestEnable = d->depth_test_enable, .DepthBufferWriteEnable = d->depth_test_enable && d->depth_write_enable, - .DepthTestFunction = genX(vk_to_gen_compare_op)[d->depth_compare_op], + .DepthTestFunction = genX(vk_to_intel_compare_op)[d->depth_compare_op], .StencilTestEnable = d->stencil_test_enable, - .StencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.fail_op], - .StencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.pass_op], - .StencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.depth_fail_op], - .StencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.front.compare_op], - .BackfaceStencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.fail_op], - .BackfaceStencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.pass_op], - .BackfaceStencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.depth_fail_op], - .BackfaceStencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.back.compare_op], + .StencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.fail_op], + .StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.pass_op], + .StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.depth_fail_op], + .StencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.front.compare_op], + .BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.fail_op], + .BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.pass_op], + .BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.depth_fail_op], + .BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.back.compare_op], }; GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil); @@ -639,7 +639,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) topology = d->primitive_topology; else - topology = genX(vk_to_gen_primitive_type)[d->primitive_topology]; + topology = genX(vk_to_intel_primitive_type)[d->primitive_topology]; cmd_buffer->state.gfx.primitive_topology = topology; @@ -658,7 +658,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->state.gfx.dirty = 0; } -static uint32_t vk_to_gen_index_type(VkIndexType type) +static uint32_t vk_to_intel_index_type(VkIndexType type) { switch (type) { case VK_INDEX_TYPE_UINT8_EXT: @@ -698,7 +698,7 @@ void genX(CmdBindIndexBuffer)( cmd_buffer->state.restart_index = restart_index_for_type(indexType); anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) { - ib.IndexFormat = vk_to_gen_index_type(indexType); + ib.IndexFormat = vk_to_intel_index_type(indexType); ib.MOCS = anv_mocs(cmd_buffer->device, buffer->address.bo, ISL_SURF_USAGE_INDEX_BUFFER_BIT); -- 2.7.4