From ddcfc35f62ed3ad83b100beacb5b30394dcd9960 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Thu, 26 May 2016 11:04:07 -0700 Subject: [PATCH] i965/sklgt4: Implement depth/timestamp write w/a The stated bug describes a scenario in which a post sync write operation for depth or timestamp can be ignored. There are two workarounds suggested, the first and easier is to simply do a cs stall when we do these type of writes. The second option is to do a PIPE_CONTROL flush after the post sync but before the data is required. Generally, I believe the data written out is consumed by the application on the CPU side and so doing the easier of the two is ideal. Furthermore, these queries aren't tremendously common in the perf sensitive apps I have looked at. However, there could be cases where a shader stage might directly consume the data, and as a result option 2 may be desirable. This patch goes with the easier solution for now. gen9lp bug_de_id=2137196 By itself, this does *not* fix any of the GT4 hangs we're currently experiencing. Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Reviewed-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_queryobj.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index f32721b..7baa213 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -56,7 +56,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) PIPE_CONTROL_STALL_AT_SCOREBOARD); } - brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_TIMESTAMP, + uint32_t flags = PIPE_CONTROL_WRITE_TIMESTAMP; + + if (brw->gen == 9 && brw->gt == 4) + flags |= PIPE_CONTROL_CS_STALL; + + brw_emit_pipe_control_write(brw, flags, query_bo, idx * sizeof(uint64_t), 0, 0); } @@ -66,9 +71,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx) { - brw_emit_pipe_control_write(brw, - PIPE_CONTROL_WRITE_DEPTH_COUNT | - PIPE_CONTROL_DEPTH_STALL, + uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL; + + if (brw->gen == 9 && brw->gt == 4) + flags |= PIPE_CONTROL_CS_STALL; + + brw_emit_pipe_control_write(brw, flags, query_bo, idx * sizeof(uint64_t), 0, 0); } -- 2.7.4