From dd632bf527857ae47bfe7d73850fed7c9791ff7a Mon Sep 17 00:00:00 2001
From: Caio Oliveira <caio.oliveira@intel.com>
Date: Sun, 11 Sep 2022 01:01:17 -0700
Subject: [PATCH] intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg
 size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
---
 src/intel/compiler/brw_fs_thread_payload.cpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 172fdbc..123df9e 100644
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -455,15 +455,15 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
        */
       task_urb_input = brw_ud1_grf(0, 7);
    }
-   r++;
+   r += reg_unit(v.devinfo);
 
-   local_index = brw_uw8_grf(1, 0);
-   r++;
-   if (v.dispatch_width == 32)
-      r++;
+   local_index = brw_uw8_grf(r, 0);
+   r += reg_unit(v.devinfo);
+   if (v.devinfo->ver < 20 && v.dispatch_width == 32)
+      r += reg_unit(v.devinfo);
 
    inline_parameter = brw_ud1_grf(r, 0);
-   r++;
+   r += reg_unit(v.devinfo);
 
    num_regs = r;
 }
-- 
2.7.4