From dd4151504a798974c1e5c0de585dab64dc5f8165 Mon Sep 17 00:00:00 2001 From: Zlatko Buljan Date: Thu, 21 Apr 2016 11:32:40 +0000 Subject: [PATCH] [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980 --- llvm/lib/Target/Mips/MipsInstrInfo.td | 11 ++++++----- llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 4 ++++ llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 4 ++++ llvm/test/MC/Mips/micromips32r6/invalid.s | 12 ++++++++++++ llvm/test/MC/Mips/micromips32r6/valid.s | 4 ++++ llvm/test/MC/Mips/micromips64r6/invalid.s | 12 ++++++++++++ llvm/test/MC/Mips/micromips64r6/valid.s | 4 ++++ 7 files changed, 46 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 4384931..356f985 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2077,11 +2077,12 @@ def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; class TLB : InstSE<(outs), (ins), asmstr, [], NoItinerary, FrmOther, asmstr>; -def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; -def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; -def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; -def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; - +let AdditionalPredicates = [NotInMicroMips] in { + def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; + def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; + def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; + def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; +} class CacheOp : InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index edc5a10..955dc4d2 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -298,3 +298,7 @@ 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 +0x00 0x00 0x03 0x7c # CHECK: tlbp +0x00 0x00 0x13 0x7c # CHECK: tlbr +0x00 0x00 0x23 0x7c # CHECK: tlbwi +0x00 0x00 0x33 0x7c # CHECK: tlbwr diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 8b2caaf..f02a411 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -225,3 +225,7 @@ 0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5 0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5 +0x00 0x00 0x03 0x7c # CHECK: tlbp +0x00 0x00 0x13 0x7c # CHECK: tlbr +0x00 0x00 0x23 0x7c # CHECK: tlbwi +0x00 0x00 0x33 0x7c # CHECK: tlbwr diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index 4af8da9..24e5a14 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -137,3 +137,15 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index e9550ff..63ec604 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -309,3 +309,7 @@ mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] + tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] + tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] + tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] + tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index 9a75f20..42f3151 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -162,3 +162,15 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index 503517a..bcc2a21 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -220,5 +220,9 @@ a: daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f] dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb] dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb] + tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] + tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] + tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] + tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] 1: -- 2.7.4