From dcef5e0c376c9ef558186ca8939b857bf7f76d56 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 25 Aug 2020 11:42:42 -0500 Subject: [PATCH] [Hexagon] Remove (redundant) HexagonISelLowering::isHvxOperation(SDValue) Use isHvxOperation(SDNode*) instead. --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 6 +++--- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 - llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 11 ----------- 3 files changed, 3 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index b938aa1..90873fc 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3025,7 +3025,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR) return LowerINLINEASM(Op, DAG); - if (isHvxOperation(Op)) { + if (isHvxOperation(Op.getNode())) { // If HVX lowering returns nothing, try the default lowering. if (SDValue V = LowerHvxOperation(Op, DAG)) return V; @@ -3132,13 +3132,13 @@ HexagonTargetLowering::ReplaceNodeResults(SDNode *N, SDValue HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { - SDValue Op(N, 0); - if (isHvxOperation(Op)) { + if (isHvxOperation(N)) { if (SDValue V = PerformHvxDAGCombine(N, DCI)) return V; return SDValue(); } + SDValue Op(N, 0); const SDLoc &dl(Op); unsigned Opc = Op.getOpcode(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 7d6e6b6..7aee7df 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -479,7 +479,6 @@ namespace HexagonISD { findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override; - bool isHvxOperation(SDValue Op) const; bool isHvxOperation(SDNode *N) const; SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const; void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl &Results, diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 5da8224..5b6fd00 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1803,17 +1803,6 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) } bool -HexagonTargetLowering::isHvxOperation(SDValue Op) const { - // If the type of the result, or any operand type are HVX vector types, - // this is an HVX operation. - return Subtarget.isHVXVectorType(ty(Op), true) || - llvm::any_of(Op.getNode()->ops(), - [this] (SDValue V) { - return Subtarget.isHVXVectorType(ty(V), true); - }); -} - -bool HexagonTargetLowering::isHvxOperation(SDNode *N) const { // If the type of any result, or any operand type are HVX vector types, // this is an HVX operation. -- 2.7.4