From dcee14979f54acf61d73a1a98823a274cbd9fdd4 Mon Sep 17 00:00:00 2001 From: "fschneider@chromium.org" Date: Mon, 26 Oct 2009 14:38:22 +0000 Subject: [PATCH] Generate more compact XOR on 64-bit architecture when using xor to zero out registers. When using xor to zero a 64-bit register, generate 32-bit instruction instead. (according to Intel 64-bit mode coding guidelines) previous code for zeroing RAX: xor rax, rax ==> new code for zeroing RAX: xor eax, eax The 32-bit operand form has the same semantics: It also zeroes the upper 32-bit of rax and its encoding uses 1 byte less. Review URL: http://codereview.chromium.org/330018 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3132 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/x64/assembler-x64.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h index 4f514f2aa..4fabc1f18 100644 --- a/src/x64/assembler-x64.h +++ b/src/x64/assembler-x64.h @@ -920,7 +920,11 @@ class Assembler : public Malloced { void testq(Register dst, Immediate mask); void xor_(Register dst, Register src) { - arithmetic_op(0x33, dst, src); + if (dst.code() == src.code()) { + arithmetic_op_32(0x33, dst, src); + } else { + arithmetic_op(0x33, dst, src); + } } void xorl(Register dst, Register src) { -- 2.34.1