From dcdf3ddff57edba3d57ed7983a74e27e09d6869b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 26 Nov 2018 17:17:07 +0000 Subject: [PATCH] AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576 --- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 4 +-- .../CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 23 ++++++------- .../CodeGen/AMDGPU/spill-empty-live-interval.mir | 39 +++++++++------------- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 14 +++----- 4 files changed, 32 insertions(+), 48 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll index bf2f5d38..3a48ffd 100644 --- a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll +++ b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll @@ -48,8 +48,8 @@ entry: ; GCN: v_readlane_b32 ; GCN-NOT: v_readlane_b32 s32 -; GCN: buffer_load_dword v32, -; GCN: buffer_load_dword v33, +; GCN-DAG: buffer_load_dword v32, +; GCN-DAG: buffer_load_dword v33, ; GCN: s_sub_u32 s32, s32, 0xc00{{$}} ; GCN: s_setpc_b64 define void @void_func_byval_struct_non_leaf(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 { diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir index be8b207..9481e98 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir @@ -75,23 +75,22 @@ name: sgpr_spill_wrong_stack_id tracksRegLiveness: true frameInfo: - adjustsStack: false hasCalls: true body: | - bb.0.bb: - %8:sreg_32_xm0 = COPY $sgpr5 - %4:vreg_64 = IMPLICIT_DEF - %3:vgpr_32 = FLAT_LOAD_DWORD %4, 0, 0, 0, implicit $exec, implicit $flat_scr - %5:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc + bb.0: + %0:sreg_32_xm0 = COPY $sgpr5 + %1:vreg_64 = IMPLICIT_DEF + %2:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr + %3:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 - dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 - $sgpr5 = COPY %8 - %12:sreg_32_xm0 = COPY $sgpr5 + dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 + $sgpr5 = COPY %0 + %4:sreg_32_xm0 = COPY $sgpr5 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 - $vgpr0 = COPY %3 - dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0 - $sgpr5 = COPY %12 + $vgpr0 = COPY %2 + dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0 + $sgpr5 = COPY %4 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ... diff --git a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir index 32b4f15..384042f 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s # https://bugs.llvm.org/show_bug.cgi?id=33620 --- @@ -10,7 +10,7 @@ # CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec # CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5) # CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec -# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec +# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec # CHECK: S_NOP 0, implicit %6.sub1 # CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5) @@ -19,20 +19,16 @@ name: expecting_non_empty_interval tracksRegLiveness: true -registers: - - { id: 0, class: vreg_64, preferred-register: '' } - - { id: 1, class: vgpr_32, preferred-register: '' } - - { id: 2, class: vgpr_32, preferred-register: '' } - - { id: 3, class: vreg_64, preferred-register: '' } body: | bb.0: successors: %bb.1 - undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit $exec - undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit $exec - dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit $exec + + undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $exec + undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec + dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $exec bb.1: - S_NOP 0, implicit %3.sub1 + S_NOP 0, implicit %2.sub1 S_NOP 0, implicit %0.sub1 S_NOP 0, implicit undef %0.sub0 @@ -44,29 +40,24 @@ body: | # CHECK-LABEL: name: rematerialize_empty_interval_has_reference # CHECK-NOT: MOV -# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec +# CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec # CHECK: bb.1: -# CHECK-NEXT: S_NOP 0, implicit %3.sub2 -# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0 -# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec -# CHECK-NEXT: S_NOP 0, implicit %4.sub2 +# CHECK-NEXT: S_NOP 0, implicit %1.sub2 +# CHECK-NEXT: S_NOP 0, implicit undef %4.sub0 +# CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: S_NOP 0, implicit %2.sub2 name: rematerialize_empty_interval_has_reference tracksRegLiveness: true -registers: - - { id: 0, class: vreg_128, preferred-register: '' } - - { id: 1, class: vgpr_32, preferred-register: '' } - - { id: 2, class: vgpr_32, preferred-register: '' } - - { id: 3, class: vreg_128, preferred-register: '' } body: | bb.0: successors: %bb.1 - undef %0.sub2 = V_MOV_B32_e32 0, implicit $exec - undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit $exec + undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec + undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec bb.1: - S_NOP 0, implicit %3.sub2 + S_NOP 0, implicit %1.sub2 S_NOP 0, implicit undef %0.sub0 S_NOP 0, implicit %0.sub2 diff --git a/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir index 68c8b31..559c0d4 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir @@ -17,18 +17,12 @@ name: no_merge_sgpr_vgpr_spill_slot tracksRegLiveness: true -registers: - - { id: 0, class: vgpr_32 } - - { id: 1, class: sreg_32_xm0_xexec } - - { id: 2, class: vgpr_32 } - - { id: 3, class: sreg_32_xm0_xexec } - body: | bb.0: - %0 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec - %2 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec + %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec + %2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec S_NOP 0, implicit %0 - %1 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 - %3 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 + %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 + %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 S_NOP 0, implicit %1 ... -- 2.7.4