From dbea1a1e51f0b5a2185c7393c294a460b759693d Mon Sep 17 00:00:00 2001 From: Hrvoje Varga Date: Thu, 24 Mar 2016 06:05:35 +0000 Subject: [PATCH] [mips][microMIPS] Fix for "Cannot copy registers" assertion Differential Revision: http://reviews.llvm.org/D17068 llvm-svn: 264245 --- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 16 ++++++++-------- llvm/lib/Target/Mips/MipsMachineFunction.cpp | 4 +++- llvm/lib/Target/Mips/MipsRegisterInfo.td | 6 ++++++ llvm/test/CodeGen/Mips/micromips-addiu.ll | 3 +++ llvm/test/CodeGen/Mips/micromips-andi.ll | 3 +++ llvm/test/CodeGen/Mips/micromips-gp-rc.ll | 3 +++ 6 files changed, 26 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 0fe9b24..3557a48 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -49,7 +49,7 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass { class mem_mm_4_generic : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPRMM16, simm4); + let MIOperandInfo = (ops ptr_rc, simm4); let OperandType = "OPERAND_MEMORY"; let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand; } @@ -75,7 +75,7 @@ def MicroMipsMemSPAsmOperand : AsmOperandClass { def mem_mm_sp_imm5_lsl2 : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32:$base, simm5:$offset); + let MIOperandInfo = (ops ptr_rc:$base, simm5:$offset); let OperandType = "OPERAND_MEMORY"; let ParserMatchClass = MicroMipsMemSPAsmOperand; let EncoderMethod = "getMemEncodingMMSPImm5Lsl2"; @@ -90,7 +90,7 @@ def mem_mm_gp_imm7_lsl2 : Operand { def mem_mm_9 : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32, simm9); + let MIOperandInfo = (ops ptr_rc, simm9); let EncoderMethod = "getMemEncodingMMImm9"; let ParserMatchClass = MipsMemAsmOperand; let OperandType = "OPERAND_MEMORY"; @@ -98,7 +98,7 @@ def mem_mm_9 : Operand { def mem_mm_12 : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32, simm12); + let MIOperandInfo = (ops ptr_rc, simm12); let EncoderMethod = "getMemEncodingMMImm12"; let ParserMatchClass = MipsMemAsmOperand; let OperandType = "OPERAND_MEMORY"; @@ -106,7 +106,7 @@ def mem_mm_12 : Operand { def mem_mm_16 : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32, simm16); + let MIOperandInfo = (ops ptr_rc, simm16); let EncoderMethod = "getMemEncodingMMImm16"; let ParserMatchClass = MipsMemAsmOperand; let OperandType = "OPERAND_MEMORY"; @@ -122,7 +122,7 @@ def MipsMemUimm4AsmOperand : AsmOperandClass { def mem_mm_4sp : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32, uimm8); + let MIOperandInfo = (ops ptr_rc, uimm8); let EncoderMethod = "getMemEncodingMMImm4sp"; let ParserMatchClass = MipsMemUimm4AsmOperand; let OperandType = "OPERAND_MEMORY"; @@ -203,7 +203,7 @@ def movep_regpair : Operand { let ParserMatchClass = MovePRegPairAsmOperand; let PrintMethod = "printRegisterList"; let DecoderMethod = "DecodeMovePRegPair"; - let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd); + let MIOperandInfo = (ops ptr_rc, ptr_rc); } class MovePMM16 : @@ -224,7 +224,7 @@ def regpair : Operand { let ParserMatchClass = RegPairAsmOperand; let PrintMethod = "printRegisterPair"; let DecoderMethod = "DecodeRegPairOperand"; - let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd); + let MIOperandInfo = (ops ptr_rc, ptr_rc); } class StorePairMM(MF.getTarget()) .getABI() .IsN64() diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index 02bcac5..939debc 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -330,6 +330,12 @@ def GPR64 : RegisterClass<"Mips", [i64], 64, (add // Reserved K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; +def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add + // Callee save + S0_64, S1_64, + // Return Values and Arguments + V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>; + def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, diff --git a/llvm/test/CodeGen/Mips/micromips-addiu.ll b/llvm/test/CodeGen/Mips/micromips-addiu.ll index e0743c9..7e30ae1 100644 --- a/llvm/test/CodeGen/Mips/micromips-addiu.ll +++ b/llvm/test/CodeGen/Mips/micromips-addiu.ll @@ -1,5 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies +; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/micromips-andi.ll b/llvm/test/CodeGen/Mips/micromips-andi.ll index cd7a794..cada8c4 100644 --- a/llvm/test/CodeGen/Mips/micromips-andi.ll +++ b/llvm/test/CodeGen/Mips/micromips-andi.ll @@ -1,5 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies +; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll index f139f7a..e27209a 100644 --- a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll +++ b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll @@ -1,5 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies +; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @g = external global i32 -- 2.7.4