From db95031d8f753c5112c43d7ea367ef92053321b1 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 11 Jan 2022 13:52:12 +0100 Subject: [PATCH] media: camss: Point sm8250 at the correct vdda regulators Reviewing the RB5 schematic its clear that we have missed out on defining both of the power-rails associated with the CSI PHY. Other PHYs such as the UFS, PCIe and USB connect to these rails and define each regulator individually. This means if we were to switch off the other various PHYs which enable these rails, the CAMSS would not appropriately power-on the CSI PHY. Reviewed-by: Robert Foss Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/qcom/camss/camss.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index c23d7b0..79ad82e 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -723,7 +723,7 @@ static const struct resources csiphy_res_8250[] = { static const struct resources csid_res_8250[] = { /* CSID0 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -735,7 +735,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID1 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -747,7 +747,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID2 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -758,7 +758,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID3 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, -- 2.7.4