From db5e6663044fe40f6479abf7efafd604ef8bdc42 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 15 Jul 2016 13:54:20 +0000 Subject: [PATCH] Revert r275141 - Mips: Avoid implicit iterator conversions, NFC It appears to have caused some failures in our buildbots. llvm-svn: 275562 --- llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 78 +++++++++++++------------ llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 6 +- llvm/lib/Target/Mips/MipsHazardSchedule.cpp | 4 +- llvm/lib/Target/Mips/MipsInstrInfo.cpp | 12 ++-- llvm/lib/Target/Mips/MipsInstrInfo.h | 2 +- llvm/lib/Target/Mips/MipsLongBranch.cpp | 6 +- 6 files changed, 57 insertions(+), 51 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 1ea48e0..b58c886 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -369,7 +369,7 @@ namespace { void doInitialPlacement(std::vector &CPEMIs); CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI); - unsigned getCPELogAlign(const MachineInstr &CPEMI); + unsigned getCPELogAlign(const MachineInstr *CPEMI); void initializeFunctionInfo(const std::vector &CPEMIs); unsigned getOffsetOf(MachineInstr *MI) const; unsigned getUserOffset(CPUser&) const; @@ -381,7 +381,7 @@ namespace { const CPUser &U); void computeBlockSize(MachineBasicBlock *MBB); - MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI); + MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI); void updateForInsertedWaterBlock(MachineBasicBlock *NewBB); void adjustBBOffsetsAfter(MachineBasicBlock *BB); bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI); @@ -620,14 +620,14 @@ MipsConstantIslands::CPEntry /// getCPELogAlign - Returns the required alignment of the constant pool entry /// represented by CPEMI. Alignment is measured in log2(bytes) units. -unsigned MipsConstantIslands::getCPELogAlign(const MachineInstr &CPEMI) { - assert(CPEMI.getOpcode() == Mips::CONSTPOOL_ENTRY); +unsigned MipsConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) { + assert(CPEMI && CPEMI->getOpcode() == Mips::CONSTPOOL_ENTRY); // Everything is 4-byte aligned unless AlignConstantIslands is set. if (!AlignConstantIslands) return 2; - unsigned CPI = CPEMI.getOperand(1).getIndex(); + unsigned CPI = CPEMI->getOperand(1).getIndex(); assert(CPI < MCP->getConstants().size() && "Invalid constant pool index."); unsigned Align = MCP->getConstants()[CPI].getAlignment(); assert(isPowerOf2_32(Align) && "Invalid CPE alignment"); @@ -654,17 +654,21 @@ initializeFunctionInfo(const std::vector &CPEMIs) { adjustBBOffsetsAfter(&MF->front()); // Now go back through the instructions and build up our data structures. - for (MachineBasicBlock &MBB : *MF) { + for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end(); + MBBI != E; ++MBBI) { + MachineBasicBlock &MBB = *MBBI; + // If this block doesn't fall through into the next MBB, then this is // 'water' that a constant pool island could be placed. if (!BBHasFallthrough(&MBB)) WaterList.push_back(&MBB); - for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); + I != E; ++I) { + if (I->isDebugValue()) continue; - int Opc = MI.getOpcode(); - if (MI.isBranch()) { + int Opc = I->getOpcode(); + if (I->isBranch()) { bool isCond = false; unsigned Bits = 0; unsigned Scale = 1; @@ -733,7 +737,7 @@ initializeFunctionInfo(const std::vector &CPEMIs) { } // Record this immediate branch. unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale; - ImmBranches.push_back(ImmBranch(&MI, MaxOffs, isCond, UOpc)); + ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc)); } if (Opc == Mips::CONSTPOOL_ENTRY) @@ -741,8 +745,8 @@ initializeFunctionInfo(const std::vector &CPEMIs) { // Scan the instructions for constant pool operands. - for (unsigned op = 0, e = MI.getNumOperands(); op != e; ++op) - if (MI.getOperand(op).isCPI()) { + for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) + if (I->getOperand(op).isCPI()) { // We found one. The addressing mode tells us the max displacement // from the PC that this instruction permits. @@ -771,12 +775,12 @@ initializeFunctionInfo(const std::vector &CPEMIs) { break; } // Remember that this is a user of a CP entry. - unsigned CPI = MI.getOperand(op).getIndex(); + unsigned CPI = I->getOperand(op).getIndex(); MachineInstr *CPEMI = CPEMIs[CPI]; unsigned MaxOffs = ((1 << Bits)-1) * Scale; unsigned LongFormMaxOffs = ((1 << LongFormBits)-1) * LongFormScale; - CPUsers.push_back(CPUser(&MI, CPEMI, MaxOffs, NegOk, LongFormMaxOffs, - LongFormOpcode)); + CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, + LongFormMaxOffs, LongFormOpcode)); // Increment corresponding CPEntry reference count. CPEntry *CPE = findConstPoolEntry(CPI, CPEMI); @@ -800,8 +804,10 @@ void MipsConstantIslands::computeBlockSize(MachineBasicBlock *MBB) { BasicBlockInfo &BBI = BBInfo[MBB->getNumber()]; BBI.Size = 0; - for (const MachineInstr &MI : *MBB) - BBI.Size += TII->GetInstSizeInBytes(MI); + for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; + ++I) + BBI.Size += TII->GetInstSizeInBytes(I); + } /// getOffsetOf - Return the current offset of the specified machine instruction @@ -818,7 +824,7 @@ unsigned MipsConstantIslands::getOffsetOf(MachineInstr *MI) const { // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->GetInstSizeInBytes(I); } return Offset; } @@ -857,9 +863,9 @@ unsigned MipsConstantIslands::getUserOffset(CPUser &U) const { /// Split the basic block containing MI into two blocks, which are joined by /// an unconditional branch. Update data structures and renumber blocks to /// account for this change and returns the newly created block. -MachineBasicBlock * -MipsConstantIslands::splitBlockBeforeInstr(MachineInstr &MI) { - MachineBasicBlock *OrigBB = MI.getParent(); +MachineBasicBlock *MipsConstantIslands::splitBlockBeforeInstr + (MachineInstr *MI) { + MachineBasicBlock *OrigBB = MI->getParent(); // Create a new MBB for the code after the OrigBB. MachineBasicBlock *NewBB = @@ -949,7 +955,7 @@ bool MipsConstantIslands::isOffsetInRange(unsigned UserOffset, bool MipsConstantIslands::isWaterInRange(unsigned UserOffset, MachineBasicBlock* Water, CPUser &U, unsigned &Growth) { - unsigned CPELogAlign = getCPELogAlign(*U.CPEMI); + unsigned CPELogAlign = getCPELogAlign(U.CPEMI); unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign); unsigned NextBlockOffset, NextBlockAlignment; MachineFunction::const_iterator NextBlock = ++Water->getIterator(); @@ -1231,7 +1237,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, CPUser &U = CPUsers[CPUserIndex]; MachineInstr *UserMI = U.MI; MachineInstr *CPEMI = U.CPEMI; - unsigned CPELogAlign = getCPELogAlign(*CPEMI); + unsigned CPELogAlign = getCPELogAlign(CPEMI); MachineBasicBlock *UserMBB = UserMI->getParent(); const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()]; @@ -1297,12 +1303,11 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPUIndex = CPUserIndex+1; unsigned NumCPUsers = CPUsers.size(); //MachineInstr *LastIT = 0; - for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); + for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI); Offset < BaseInsertOffset; - Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { + Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); - if (CPUIndex < NumCPUsers && - CPUsers[CPUIndex].MI == static_cast(MI)) { + if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) { CPUser &U = CPUsers[CPUIndex]; if (!isOffsetInRange(Offset, EndInsertOffset, U)) { // Shift intertion point by one unit of alignment so it is within reach. @@ -1318,7 +1323,8 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, } } - NewMBB = splitBlockBeforeInstr(*--MI); + --MI; + NewMBB = splitBlockBeforeInstr(MI); } /// handleConstantPoolUser - Analyze the specified user, checking to see if it @@ -1411,7 +1417,7 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { ++NumCPEs; // Mark the basic block as aligned as required by the const-pool entry. - NewIsland->setAlignment(getCPELogAlign(*U.CPEMI)); + NewIsland->setAlignment(getCPELogAlign(U.CPEMI)); // Increase the size of the island block to account for the new entry. BBInfo[NewIsland->getNumber()].Size += Size; @@ -1445,7 +1451,7 @@ void MipsConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) { CPEBB->setAlignment(0); } else // Entries are sorted by descending alignment, so realign from the front. - CPEBB->setAlignment(getCPELogAlign(*CPEBB->begin())); + CPEBB->setAlignment(getCPELogAlign(CPEBB->begin())); adjustBBOffsetsAfter(CPEBB); // An island has only one predecessor BB and one successor BB. Check if @@ -1619,10 +1625,10 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { if (NeedSplit) { - splitBlockBeforeInstr(*MI); + splitBlockBeforeInstr(MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->GetInstSizeInBytes(&MBB->back()); BBInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BBInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -1644,14 +1650,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { .addMBB(NextBB); } Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back()); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI); MI->eraseFromParent(); adjustBBOffsetsAfter(MBB); return true; diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index 5ec1717..76361b8 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -600,9 +600,9 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { if (Filled) { // Get instruction with delay slot. - MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); + MachineBasicBlock::instr_iterator DSI(I); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && + if (InMicroMipsMode && TII->GetInstSizeInBytes(&*std::next(DSI)) == 2 && DSI->isCall()) { // If instruction in delay slot is 16b change opcode to // corresponding instruction with short delay slot. @@ -692,7 +692,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, bool InMicroMipsMode = STI.inMicroMipsMode(); const MipsInstrInfo *TII = STI.getInstrInfo(); unsigned Opcode = (*Slot).getOpcode(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && + if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*CurrI)) == 2 && (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || Opcode == Mips::PseudoReturn)) continue; diff --git a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp index 10022ba..c595c9b 100644 --- a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp @@ -137,8 +137,8 @@ bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) { if (InsertNop) { Changed = true; - MIBundleBuilder(&*I).append( - BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP))); + MIBundleBuilder(I) + .append(BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP))); NumInsertedNops++; } } diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index af018c6..46587a3 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -377,19 +377,19 @@ bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const { } /// Return the number of bytes of code the specified instruction may be. -unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { - switch (MI.getOpcode()) { +unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { + switch (MI->getOpcode()) { default: - return MI.getDesc().getSize(); + return MI->getDesc().getSize(); case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. - const MachineFunction *MF = MI.getParent()->getParent(); - const char *AsmStr = MI.getOperand(0).getSymbolName(); + const MachineFunction *MF = MI->getParent()->getParent(); + const char *AsmStr = MI->getOperand(0).getSymbolName(); return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); } case Mips::CONSTPOOL_ENTRY: // If this machine instr is a constant pool entry, its size is recorded as // operand #2. - return MI.getOperand(2).getImm(); + return MI->getOperand(2).getImm(); } } diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index ae20fe1..4a773ee 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -92,7 +92,7 @@ public: virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; /// Return the number of bytes of code the specified instruction may be. - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned GetInstSizeInBytes(const MachineInstr *MI) const; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp index e721312..8c8faf3 100644 --- a/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -179,7 +179,7 @@ void MipsLongBranch::initMBBInfo() { // Compute size of MBB. for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin(); MI != MBB->instr_end(); ++MI) - MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI); + MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); // Search for MBB's branch instruction. ReverseIter End = MBB->rend(); @@ -187,7 +187,7 @@ void MipsLongBranch::initMBBInfo() { if ((Br != End) && !Br->isIndirectBranch() && (Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC))) - MBBInfos[I].Br = &*(++Br).base(); + MBBInfos[I].Br = (++Br).base(); } } @@ -241,7 +241,7 @@ void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br, // Bundle the instruction in the delay slot to the newly created branch // and erase the original branch. assert(Br->isBundledWithSucc()); - MachineBasicBlock::instr_iterator II = Br.getInstrIterator(); + MachineBasicBlock::instr_iterator II(Br); MIBundleBuilder(&*MIB).append((++II)->removeFromBundle()); } Br->eraseFromParent(); -- 2.7.4