From db54627413fdcc96f356897e23db204557c48a80 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 24 May 2023 12:00:01 +0100 Subject: [PATCH] [MachineVerifier] Try harder to verify LiveIntervals Verify the LiveIntervals analysis after a pass that claims to preserve it, even if there are no further passes (apart from the verifier itself) that would use the analysis. Fixes https://github.com/llvm/llvm-project/issues/46217 Differential Revision: https://reviews.llvm.org/D129208 --- llvm/lib/CodeGen/MachineVerifier.cpp | 1 + llvm/test/CodeGen/AArch64/regcoal-physreg.mir | 6 +----- .../AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir | 6 +----- .../AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir | 6 +----- llvm/test/CodeGen/AMDGPU/subreg-intervals.mir | 17 ----------------- .../CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll | 4 ++-- 6 files changed, 6 insertions(+), 34 deletions(-) diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 556047f..8c5c732 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -297,6 +297,7 @@ namespace { AU.addUsedIfAvailable(); AU.addUsedIfAvailable(); AU.addUsedIfAvailable(); + AU.addUsedIfAvailable(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/test/CodeGen/AArch64/regcoal-physreg.mir b/llvm/test/CodeGen/AArch64/regcoal-physreg.mir index 05b66de..270abee 100644 --- a/llvm/test/CodeGen/AArch64/regcoal-physreg.mir +++ b/llvm/test/CodeGen/AArch64/regcoal-physreg.mir @@ -1,8 +1,4 @@ -# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing,simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s - -# FIXME: Second run of the pass is a workaround for a bug in -# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug -# 46873 +# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s --- | declare void @f2() diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir index 6658171..61a0d47 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir @@ -1,9 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra,si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s - -# FIXME: Second run of the pass is a workaround for a bug in -# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug -# 46873 +# RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s # %8 is defined at the end, but it will be used in bb.2. # Make sure we properly extend its liverange to the beginning of the bb.2. diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir index 0093473..84f9871 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir @@ -1,9 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra,si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s - -# FIXME: Second run of the pass is a workaround for a bug in -# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug -# 46873 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s # Cannot fold this without moving the def of %7 after the and. diff --git a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir index 54cd304..4cda3fe 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir @@ -3,29 +3,12 @@ # CHECK: INTERVALS # CHECK: %0 -# CHECK-LABEL: Machine code for function test0: - -# CHECK: INTERVALS -# CHECK: %0 # CHECK-LABEL: Machine code for function test1: --- | - define amdgpu_kernel void @test0() { ret void } define amdgpu_kernel void @test1() { ret void } ... --- -name: test0 -registers: - - { id: 0, class: sreg_64 } -body: | - bb.0: - S_NOP 0, implicit-def %0 - S_NOP 0, implicit %0 - - S_NOP 0, implicit-def undef %0.sub0 - S_NOP 0, implicit %0 -... ---- name: test1 registers: - { id: 0, class: sreg_64 } diff --git a/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll b/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll index bd09b03..63b2a9d 100644 --- a/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll +++ b/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll @@ -62,8 +62,8 @@ zero: ; CHECK: bb.5 ; CHECK: %3:gr64 = COPY %10 ; CHECK-LV: %4:gr64 = COPY killed %10 -; CHECK-LV: %4:gr64 = nuw ADD64ri32 %4, 8, implicit-def dead $eflags -; CHECK-LIS: %4:gr64 = LEA64r %10, 1, $noreg, 8, $noreg +; CHECK-LIS: %4:gr64 = COPY %10 +; CHECK: %4:gr64 = nuw ADD64ri32 %4, 8, implicit-def dead $eflags ; CHECK: TEST64rr killed %1, %1, implicit-def $eflags ; CHECK: JCC_1 %bb.1, 5, implicit killed $eflags ; CHECK: JMP_1 %bb.6 -- 2.7.4