From db3fc8fa0fcfa481cd8087c2ee068d1d1988c3a2 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:54 +0200 Subject: [PATCH] ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188 Add the vpu node to the common rk3xxx.dtsi and only the powerdomain property to the SoC specific device trees. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-12-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 4 ++++ arch/arm/boot/dts/rk3188.dtsi | 5 +++++ arch/arm/boot/dts/rk3xxx.dtsi | 12 ++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b15cbbe..f5a665b 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -868,6 +868,10 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b36fcdd..793a1b9 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -801,6 +801,11 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index f9bbc24..616a828 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -47,6 +47,18 @@ status = "disabled"; }; + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; -- 2.7.4