From db2c830d467db6e10e30729f16401ecd4b6480aa Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Wed, 18 Nov 2015 10:07:24 -0700 Subject: [PATCH] staging: comedi: adv_pci_dio: use common defines for PCI-1739/175[01] registers These boards use the same offsets for the interrupt control registers. For aesthetics, remove the current defines and use common ones. Fix the switch() in pci_dio_reset() to use common code. Signed-off-by: H Hartley Sweeten Reviewed-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adv_pci_dio.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/staging/comedi/drivers/adv_pci_dio.c b/drivers/staging/comedi/drivers/adv_pci_dio.c index fae0a0b..c216f39 100644 --- a/drivers/staging/comedi/drivers/adv_pci_dio.c +++ b/drivers/staging/comedi/drivers/adv_pci_dio.c @@ -57,17 +57,10 @@ enum hw_cards_id { #define PCI173X_INT_RF_REG 0x0c /* R/W: falling/rising edge */ #define PCI173X_INT_CLR_REG 0x10 /* R/W: clear */ -/* Advantech PCI-1739U */ -#define PCI1739_ICR 32 /* W: Interrupt control register */ -#define PCI1739_ISR 32 /* R: Interrupt status register */ - -/* Advantech PCI-1750 */ -#define PCI1750_ICR 32 /* W: Interrupt control register */ -#define PCI1750_ISR 32 /* R: Interrupt status register */ +/* PCI-1739U, PCI-1750, PCI1751 interrupt control registers */ +#define PCI1750_INT_REG 0x20 /* R/W: status/control */ /* Advantech PCI-1751/3/3E */ -#define PCI1751_ICR 32 /* W: Interrupt control register */ -#define PCI1751_ISR 32 /* R: Interrupt status register */ #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */ #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */ #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */ @@ -313,11 +306,9 @@ static int pci_dio_reset(struct comedi_device *dev) outb(0, dev->iobase + PCI173X_INT_RF_REG); break; case TYPE_PCI1739: - outb(0x88, dev->iobase + PCI1739_ICR); - break; case TYPE_PCI1750: case TYPE_PCI1751: - outb(0x88, dev->iobase + PCI1750_ICR); + outb(0x88, dev->iobase + PCI1750_INT_REG); break; case TYPE_PCI1753E: outb(0x88, dev->iobase + PCI1753E_ICR0); -- 2.7.4