From dac5957ca934206f4b0777e62f093b08919e36a9 Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Wed, 5 Jul 2023 10:31:18 +0100 Subject: [PATCH] [AMDGPU][AsmParser][NFC] Clean up the implementation of KImmFP operands. addKImmFPOperands() duplicates the KImmFP-specific logic implemented in addLiteralImmOperand() and therefore can be removed. Part of . Reviewed By: foad Differential Revision: https://reviews.llvm.org/D154427 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 29 ---------------------- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 13 +++------- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 18 +++----------- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +-- 4 files changed, 9 insertions(+), 55 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 46c4366..cb28f8c 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -949,17 +949,6 @@ public: void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const; - template - void addKImmFPOperands(MCInst &Inst, unsigned N) const; - - void addKImmFP16Operands(MCInst &Inst, unsigned N) const { - addKImmFPOperands<16>(Inst, N); - } - - void addKImmFP32Operands(MCInst &Inst, unsigned N) const { - addKImmFPOperands<32>(Inst, N); - } - void addRegOperands(MCInst &Inst, unsigned N) const; void addRegOrImmOperands(MCInst &Inst, unsigned N) const { @@ -2269,24 +2258,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo } } -template -void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const { - APInt Literal(64, Imm.Val); - setImmKindMandatoryLiteral(); - - if (!Imm.IsFPImm) { - // We got int literal token. - Inst.addOperand(MCOperand::createImm(Literal.getLoBits(Bitwidth).getZExtValue())); - return; - } - - bool Lost; - APFloat FPLiteral(APFloat::IEEEdouble(), Literal); - FPLiteral.convert(*getFltSemantics(Bitwidth / 8), - APFloat::rmNearestTiesToEven, &Lost); - Inst.addOperand(MCOperand::createImm(FPLiteral.bitcastToAPInt().getZExtValue())); -} - void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index b974031..123de0f 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -262,16 +262,9 @@ DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) -static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { - const auto *DAsm = static_cast(Decoder); - return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); -} - -static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const MCDisassembler *Decoder) { +static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, + uint64_t Addr, + const MCDisassembler *Decoder) { const auto *DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index c50bb0a..c0ab499 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1142,29 +1142,19 @@ def exp_tgt : CustomOperand; def wait_vdst : NamedIntOperand; def wait_exp : NamedIntOperand; -class KImmMatchClass : AsmOperandClass { - let Name = "KImmFP"#size; - let PredicateMethod = "isKImmFP"#size; - let ParserMethod = "parseImm"; - let RenderMethod = "addKImmFP"#size#"Operands"; -} - -class kimmOperand : Operand { +class KImmFPOperand : ImmOperand { let OperandNamespace = "AMDGPU"; let OperandType = "OPERAND_KIMM"#vt.Size; let PrintMethod = "printU"#vt.Size#"ImmOperand"; - let ParserMatchClass = !cast("KImmFP"#vt.Size#"MatchClass"); - let DecoderMethod = "decodeOperand_f"#vt.Size#"kimm"; + let DecoderMethod = "decodeOperand_KImmFP"; } // 32-bit VALU immediate operand that uses the constant bus. -def KImmFP32MatchClass : KImmMatchClass<32>; -def f32kimm : kimmOperand; +def KImmFP32 : KImmFPOperand; // 32-bit VALU immediate operand with a 16-bit value that uses the // constant bus. -def KImmFP16MatchClass : KImmMatchClass<16>; -def f16kimm : kimmOperand; +def KImmFP16 : KImmFPOperand; class FPInputModsMatchClass : AsmOperandClass { let Name = "RegOrImmWithFP"#opSize#"InputMods"; diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index ea7ab16..481a162 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -357,7 +357,7 @@ class VOP_MADK_Base : VOPProfile <[vt, vt, vt, vt]> { } class VOP_MADAK : VOP_MADK_Base { - field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); + field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32, KImmFP16); field dag Ins32 = !if(!eq(vt.Size, 32), (ins VSrc_f32_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm), (ins VSrc_f16_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm)); @@ -383,7 +383,7 @@ def VOP_MADAK_F16_t16 : VOP_MADAK { def VOP_MADAK_F32 : VOP_MADAK ; class VOP_MADMK : VOP_MADK_Base { - field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); + field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32, KImmFP16); field dag Ins32 = !if(!eq(vt.Size, 32), (ins VSrc_f32_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1), (ins VSrc_f16_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1)); -- 2.7.4