From da4a966e1c3c0315512e1dfe5cd486722bcc0fbf Mon Sep 17 00:00:00 2001 From: Gabor Buella Date: Wed, 4 Jul 2018 13:28:39 +0000 Subject: [PATCH] NFC - Various typo fixes in tests llvm-svn: 336268 --- llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll | 4 +- llvm/test/CodeGen/AArch64/andandshift.ll | 4 +- .../CodeGen/AArch64/arm64-addr-mode-folding.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-csel.ll | 6 +- llvm/test/CodeGen/AArch64/cmpwithshort.ll | 6 +- llvm/test/CodeGen/AArch64/fast-isel-gep.ll | 2 +- .../CodeGen/ARM/GlobalISel/arm-param-lowering.ll | 2 +- llvm/test/CodeGen/ARM/atomic-op.ll | 4 +- llvm/test/CodeGen/ARM/debug-frame-large-stack.ll | 20 +++--- llvm/test/CodeGen/ARM/float-helpers.s | 8 +-- llvm/test/CodeGen/ARM/fp16.ll | 2 +- llvm/test/CodeGen/ARM/shift-combine.ll | 2 +- llvm/test/CodeGen/NVPTX/ctlz.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll | 2 +- llvm/test/CodeGen/SPARC/soft-float.ll | 6 +- llvm/test/CodeGen/WebAssembly/address-offsets.ll | 80 +++++++++++----------- llvm/test/DebugInfo/X86/mem2reg_fp80.ll | 4 +- llvm/test/MC/Disassembler/Hexagon/nv_j.txt | 2 +- .../test/Transforms/Inline/deoptimize-intrinsic.ll | 2 +- llvm/test/Transforms/LICM/loopsink.ll | 2 +- .../LoadStoreVectorizer/X86/merge-tbaa.ll | 2 +- .../Transforms/LoopInterchange/profitability.ll | 4 +- .../LoopVectorize/X86/vector_max_bandwidth.ll | 2 +- .../deopt-intrinsic-cconv.ll | 2 +- .../llvm-dwarfdump/X86/debug_line_offset.test | 10 +-- 25 files changed, 92 insertions(+), 92 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll index 08e506a..3a249e6 100644 --- a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll +++ b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll @@ -4,7 +4,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "arm64--linux-gnu" -; CHECK-LABLE: @aarch64_tree_tests_and +; CHECK-LABEL: @aarch64_tree_tests_and ; CHECK: .hword 32768 ; CHECK: .hword 32767 ; CHECK: .hword 4664 @@ -22,7 +22,7 @@ entry: ret <8 x i16> %ret } -; CHECK-LABLE: @aarch64_tree_tests_or +; CHECK-LABEL: @aarch64_tree_tests_or ; CHECK: .hword 32768 ; CHECK: .hword 32766 ; CHECK: .hword 4664 diff --git a/llvm/test/CodeGen/AArch64/andandshift.ll b/llvm/test/CodeGen/AArch64/andandshift.ll index e2c7a09..e6019b3 100644 --- a/llvm/test/CodeGen/AArch64/andandshift.ll +++ b/llvm/test/CodeGen/AArch64/andandshift.ll @@ -4,7 +4,7 @@ target triple = "arm64--linux-gnu" ; Function Attrs: nounwind readnone define i32 @test1(i8 %a) { -; CHECK-LABLE: @test1 +; CHECK-LABEL: @test1 ; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5 entry: %conv = zext i8 %a to i32 @@ -14,7 +14,7 @@ entry: ; Function Attrs: nounwind readnone define i32 @test2(i8 %a) { -; CHECK-LABLE: @test2 +; CHECK-LABEL: @test2 ; CHECK: and {{w[0-9]+}}, w0, #0xff ; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5 entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll b/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll index 6eaf75c..da1f366 100644 --- a/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll +++ b/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll @@ -8,7 +8,7 @@ define i32 @fct(i32 %i1, i32 %i2) { ; Sign extension is used more than once, thus it should not be folded. ; CodeGenPrepare is not sharing sext across uses, thus this is folded because ; of that. -; _CHECK-NOT_: , sxtw] +; _CHECK-NOT: , sxtw] entry: %idxprom = sext i32 %i1 to i64 %0 = load i8*, i8** @block, align 8 diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll index 3e24610..ed31328 100644 --- a/llvm/test/CodeGen/AArch64/arm64-csel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll @@ -79,9 +79,9 @@ define i32 @foo7(i32 %a, i32 %b) nounwind { entry: ; CHECK-LABEL: foo7: ; CHECK: sub -; CHECK-next: adds -; CHECK-next: csneg -; CHECK-next: b +; CHECK-NEXT: adds +; CHECK-NEXT: csneg +; CHECK-NEXT: b %sub = sub nsw i32 %a, %b %cmp = icmp sgt i32 %sub, -1 %sub3 = sub nsw i32 0, %sub diff --git a/llvm/test/CodeGen/AArch64/cmpwithshort.ll b/llvm/test/CodeGen/AArch64/cmpwithshort.ll index 8a94689..a0475c4 100644 --- a/llvm/test/CodeGen/AArch64/cmpwithshort.ll +++ b/llvm/test/CodeGen/AArch64/cmpwithshort.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s define i16 @test_1cmp_signed_1(i16* %ptr1) { -; CHECK-LABLE: @test_1cmp_signed_1 +; CHECK-LABEL: @test_1cmp_signed_1 ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: @@ -16,7 +16,7 @@ if.then: } define i16 @test_1cmp_signed_2(i16* %ptr1) { -; CHECK-LABLE: @test_1cmp_signed_2 +; CHECK-LABEL: @test_1cmp_signed_2 ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: @@ -31,7 +31,7 @@ if.then: } define i16 @test_1cmp_unsigned_1(i16* %ptr1) { -; CHECK-LABLE: @test_1cmp_unsigned_1 +; CHECK-LABEL: @test_1cmp_unsigned_1 ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: diff --git a/llvm/test/CodeGen/AArch64/fast-isel-gep.ll b/llvm/test/CodeGen/AArch64/fast-isel-gep.ll index 0cb1fd8..6654769 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-gep.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-gep.ll @@ -34,7 +34,7 @@ define i32* @test_array3(i32* %a) { define i32* @test_array4(i32* %a) { ; CHECK-LABEL: test_array4 ; CHECK: mov [[REG:x[0-9]+]], #4104 -; CHECK-NEXR: add x0, x0, [[REG]] +; CHECK-NEXT: add x0, x0, [[REG]] %1 = getelementptr inbounds i32, i32* %a, i64 1026 ret i32* %1 } diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll index 0c2119f..ff307af 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll @@ -30,7 +30,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]] -; CHECK-DxAG: $r2 = COPY [[BVREG]] +; CHECK-DAG: $r2 = COPY [[BVREG]] ; CHECK-DAG: $r3 = COPY [[AVREG]] ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll index a374180..8ab2026 100644 --- a/llvm/test/CodeGen/ARM/atomic-op.ll +++ b/llvm/test/CodeGen/ARM/atomic-op.ll @@ -396,9 +396,9 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) { ; CHECK-T1-M0: str r3, [r2] ; CHECK-BAREMETAL-NOT: dmb -; CHECK-BAREMTEAL: str r1, [r0] +; CHECK-BAREMETAL: str r1, [r0] ; CHECK-BAREMETAL-NOT: dmb -; CHECK-BAREMTEAL: str r3, [r2] +; CHECK-BAREMETAL: str r3, [r2] ret void } diff --git a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll index 22869c2..02a6260 100644 --- a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll +++ b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll @@ -35,16 +35,16 @@ define void @test2() { ; CHECK-ARM: sub sp, sp, #4096 ; CHECK-ARM: .cfi_endproc -; CHECK-ARM-FP_ELIM-LABEL: test2: -; CHECK-ARM-FP_ELIM: .cfi_startproc -; CHECK-ARM-FP_ELIM: push {r4, r5} -; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 8 -; CHECK-ARM-FP_ELIM: .cfi_offset 54, -4 -; CHECK-ARM-FP_ELIM: .cfi_offset r4, -8 -; CHECK-ARM-FP_ELIM: sub sp, sp, #72 -; CHECK-ARM-FP_ELIM: sub sp, sp, #4096 -; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 4176 -; CHECK-ARM-FP_ELIM: .cfi_endproc +; CHECK-ARM-FP-ELIM-LABEL: test2: +; CHECK-ARM-FP-ELIM: .cfi_startproc +; CHECK-ARM-FP-ELIM: push {r4, r5} +; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 8 +; CHECK-ARM-FP-ELIM: .cfi_offset 54, -4 +; CHECK-ARM-FP-ELIM: .cfi_offset r4, -8 +; CHECK-ARM-FP-ELIM: sub sp, sp, #72 +; CHECK-ARM-FP-ELIM: sub sp, sp, #4096 +; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 4176 +; CHECK-ARM-FP-ELIM: .cfi_endproc define i32 @test3() { %retval = alloca i32, align 4 diff --git a/llvm/test/CodeGen/ARM/float-helpers.s b/llvm/test/CodeGen/ARM/float-helpers.s index c861f1f..0a9f249 100644 --- a/llvm/test/CodeGen/ARM/float-helpers.s +++ b/llvm/test/CodeGen/ARM/float-helpers.s @@ -20,14 +20,14 @@ ; * all functions use base AAPCS ; * floating point instructions permitted, so __aeabi_ helpers only ; expected when there is no available instruction. -; CHECK-HARD-FP-SP -mfloat-abi=hardfp (single precision instructions) +; CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions) ; * all non Runtime ABI helper functions use AAPCS VFP ; * floating point instructions permitted, so __aeabi_ helpers only ; expected when there is no available instruction. -; CHECK-HARD-FP-DP -mfloat-abi=hardfp (double precision instructions) -; CHECK-HARD_FP_SPONLY -mfloat-abi=hardfp (double precision but single +; CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions) +; CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single ; precision only FPU) -; * as CHECK-HARD-FP-SP, but we split up the double precision helper +; * as CHECK-HARDFP-SP, but we split up the double precision helper ; functions so we can test a single precision only FPU, which has to use ; helper function for all double precision operations. diff --git a/llvm/test/CodeGen/ARM/fp16.ll b/llvm/test/CodeGen/ARM/fp16.ll index b2cccd8..04e02bf 100644 --- a/llvm/test/CodeGen/ARM/fp16.ll +++ b/llvm/test/CodeGen/ARM/fp16.ll @@ -29,7 +29,7 @@ entry: ; CHECK-HARDFLOAT-EABI: __aeabi_h2f ; CHECK-HARDFLOAT-GNU: __gnu_h2f_ieee ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-ARMv8: vcvtb.f32.f16 +; CHECK-ARMV8: vcvtb.f32.f16 ; CHECK-SOFTFLOAT-EABI: __aeabi_h2f ; CHECK-SOFTFLOAT-GNU: __gnu_h2f_ieee %3 = tail call float @llvm.convert.from.fp16.f32(i16 %1) diff --git a/llvm/test/CodeGen/ARM/shift-combine.ll b/llvm/test/CodeGen/ARM/shift-combine.ll index 24c392cb..dbd9a41 100644 --- a/llvm/test/CodeGen/ARM/shift-combine.ll +++ b/llvm/test/CodeGen/ARM/shift-combine.ll @@ -9,7 +9,7 @@ define i32 @test_lshr_and1(i32 %x) { entry: -;CHECK-LABLE: test_lshr_and1: +;CHECK-LABEL: test_lshr_and1: ;CHECK-COMMON: movw r1, :lower16:array ;CHECK-COMMON-NEXT: and r0, r0, #12 ;CHECK-COMMON-NEXT: movt r1, :upper16:array diff --git a/llvm/test/CodeGen/NVPTX/ctlz.ll b/llvm/test/CodeGen/NVPTX/ctlz.ll index 7aa29fe..13eef24 100644 --- a/llvm/test/CodeGen/NVPTX/ctlz.ll +++ b/llvm/test/CodeGen/NVPTX/ctlz.ll @@ -108,7 +108,7 @@ define i16 @myctlz_ret16_2(i16 %a) { define void @myctlz_store16(i16 %a, i16* %b) { ; CHECK: ld.param. ; CHECK-NEXT: cvt.u32.u16 -; CHECK-NET: clz.b32 +; CHECK-NEXT: clz.b32 ; CHECK-DAG: cvt.u16.u32 ; CHECK-DAG: sub. ; CHECK: st.{{[a-z]}}16 @@ -121,7 +121,7 @@ define void @myctlz_store16(i16 %a, i16* %b) { define void @myctlz_store16_2(i16 %a, i16* %b) { ; CHECK: ld.param. ; CHECK-NEXT: cvt.u32.u16 -; CHECK-NET: clz.b32 +; CHECK-NEXT: clz.b32 ; CHECK-DAG: cvt.u16.u32 ; CHECK-DAG: sub. ; CHECK: st.{{[a-z]}}16 diff --git a/llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll b/llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll index 50f6f9a..3efefb9 100644 --- a/llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll +++ b/llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll @@ -30,7 +30,7 @@ define <2 x i64> @test_vsrd(<2 x i64> %x, <2 x i64> %y) nounwind readnone { define <2 x i64> @test_vsrad(<2 x i64> %x, <2 x i64> %y) nounwind readnone { %tmp = ashr <2 x i64> %x, %y ret <2 x i64> %tmp -; CHECK-LABER: @test_vsrad +; CHECK-LABEL: @test_vsrad ; CHECK: vsrad 2, 2, 3 } diff --git a/llvm/test/CodeGen/SPARC/soft-float.ll b/llvm/test/CodeGen/SPARC/soft-float.ll index 5828044..35cbbb1 100644 --- a/llvm/test/CodeGen/SPARC/soft-float.ll +++ b/llvm/test/CodeGen/SPARC/soft-float.ll @@ -151,21 +151,21 @@ define i1 @test_netf2(fp128 %a, fp128 %b) #0 { } define i1 @test_gesf2(float %a, float %b) #0 { - ; CHECK-LABLE: test_gesf2: + ; CHECK-LABEL: test_gesf2: ; CHECK: call __gesf2 %cmp = fcmp oge float %a, %b ret i1 %cmp } define i1 @test_gedf2(double %a, double %b) #0 { - ; CHECK-LABLE: test_gedf2: + ; CHECK-LABEL: test_gedf2: ; CHECK: call __gedf2 %cmp = fcmp oge double %a, %b ret i1 %cmp } define i1 @test_getf2(fp128 %a, fp128 %b) #0 { - ; CHECK-LABLE: test_getf2: + ; CHECK-LABEL: test_getf2: ; CHECK: call __getf2 %cmp = fcmp oge fp128 %a, %b ret i1 %cmp diff --git a/llvm/test/CodeGen/WebAssembly/address-offsets.ll b/llvm/test/CodeGen/WebAssembly/address-offsets.ll index 9fdbd54..6950fc9 100644 --- a/llvm/test/CodeGen/WebAssembly/address-offsets.ll +++ b/llvm/test/CodeGen/WebAssembly/address-offsets.ll @@ -36,9 +36,9 @@ define i32 @load_test0_noinbounds() { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test1(i32 %n) { %add = add nsw i32 %n, 10 %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -50,9 +50,9 @@ define i32 @load_test1(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test2(i32 %n) { %add = add nsw i32 10, %n %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -64,9 +64,9 @@ define i32 @load_test2(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test3(i32 %n) { %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10 @@ -78,9 +78,9 @@ define i32 @load_test3(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test4(i32 %n) { %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n %t = load i32, i32* %add.ptr, align 4 @@ -91,9 +91,9 @@ define i32 @load_test4(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test5(i32 %n) { %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n %t = load i32, i32* %add.ptr, align 4 @@ -104,9 +104,9 @@ define i32 @load_test5(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test6(i32 %n) { %add = add nsw i32 %n, 10 %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -118,9 +118,9 @@ define i32 @load_test6(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test7(i32 %n) { %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10 @@ -132,9 +132,9 @@ define i32 @load_test7(i32 %n) { ; CHECK-NEXT: param i32{{$}} ; CHECK-NEXT: result i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} -; CHECK-NEX T: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.load $push2=, g+40($pop1){{$}} -; CHECK-NEX T: return $pop2{{$}} +; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push2=, g+40($pop1){{$}} +; CHECK-NEXT: return $pop2{{$}} define i32 @load_test8(i32 %n) { %add = add nsw i32 10, %n %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -378,8 +378,8 @@ define void @store_test0_noinbounds(i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test1(i32 %n, i32 %i) { %add = add nsw i32 %n, 10 %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -391,8 +391,8 @@ define void @store_test1(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test2(i32 %n, i32 %i) { %add = add nsw i32 10, %n %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -404,8 +404,8 @@ define void @store_test2(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test3(i32 %n, i32 %i) { %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10 @@ -417,8 +417,8 @@ define void @store_test3(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test4(i32 %n, i32 %i) { %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n store i32 %i, i32* %add.ptr, align 4 @@ -429,8 +429,8 @@ define void @store_test4(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test5(i32 %n, i32 %i) { %add.ptr = getelementptr inbounds i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @g, i32 0, i32 10), i32 %n store i32 %i, i32* %add.ptr, align 4 @@ -441,8 +441,8 @@ define void @store_test5(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test6(i32 %n, i32 %i) { %add = add nsw i32 %n, 10 %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add @@ -454,8 +454,8 @@ define void @store_test6(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test7(i32 %n, i32 %i) { %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %n %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10 @@ -467,8 +467,8 @@ define void @store_test7(i32 %n, i32 %i) { ; CHECK-NEXT: param i32, i32{{$}} ; CHECK-NEXT: i32.const $push0=, 2{{$}} ; CHECK-NEXT: i32.shl $push1=, $0, $pop0{{$}} -; CHECK-NEX T: i32.store g+40($pop1), $1{{$}} -; CHECK-NEX T: return{{$}} +; CHECK-NEXT: i32.store g+40($pop1), $1{{$}} +; CHECK-NEXT: return{{$}} define void @store_test8(i32 %n, i32 %i) { %add = add nsw i32 10, %n %add.ptr = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add diff --git a/llvm/test/DebugInfo/X86/mem2reg_fp80.ll b/llvm/test/DebugInfo/X86/mem2reg_fp80.ll index fa79c61..1d71fa3 100644 --- a/llvm/test/DebugInfo/X86/mem2reg_fp80.ll +++ b/llvm/test/DebugInfo/X86/mem2reg_fp80.ll @@ -10,7 +10,7 @@ entry: br i1 undef, label %if.then, label %if.end, !dbg !16 if.then: ; preds = %entry -; CHECK-label: if.then: +; CHECK-LABEL: if.then: ; CHECK: %mul = fmul x86_fp80 ; CHECK: call void @llvm.dbg.value(metadata x86_fp80 %mul, metadata {{.*}}, metadata !DIExpression()) %mul = fmul x86_fp80 undef, undef, !dbg !18 @@ -18,7 +18,7 @@ if.then: ; preds = %entry br label %if.end, !dbg !20 if.end: ; preds = %if.then, %entry -; CHECK-label: if.end: +; CHECK-LABEL: if.end: ; CHECK: %r.0 = phi x86_fp80 ; CHECK: call void @llvm.dbg.value(metadata x86_fp80 %r.0, metadata {{.*}}, metadata !DIExpression()) %out = load x86_fp80, x86_fp80* %r, align 16, !dbg !21 diff --git a/llvm/test/MC/Disassembler/Hexagon/nv_j.txt b/llvm/test/MC/Disassembler/Hexagon/nv_j.txt index f3b7140..6fcae7c 100644 --- a/llvm/test/MC/Disassembler/Hexagon/nv_j.txt +++ b/llvm/test/MC/Disassembler/Hexagon/nv_j.txt @@ -67,7 +67,7 @@ # CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24 # CHECK: r17 = r17 -# CHECK-NETX: if (cmp.eq(r17.new,#21)) jump:t +# CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24 # CHECK: r17 = r17 # CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:nt diff --git a/llvm/test/Transforms/Inline/deoptimize-intrinsic.ll b/llvm/test/Transforms/Inline/deoptimize-intrinsic.ll index 848a9db..3d84bfc 100644 --- a/llvm/test/Transforms/Inline/deoptimize-intrinsic.ll +++ b/llvm/test/Transforms/Inline/deoptimize-intrinsic.ll @@ -97,7 +97,7 @@ define i8 @callee_with_alloca() alwaysinline { } define void @caller_with_lifetime() { -; CHECK-LABLE: @caller_with_lifetime( +; CHECK-LABEL: @caller_with_lifetime( ; CHECK: call void (...) @llvm.experimental.deoptimize.isVoid(i32 1) [ "deopt"(i8* %t.i) ] ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/LICM/loopsink.ll b/llvm/test/Transforms/LICM/loopsink.ll index 09dddb4..f9bdbae 100644 --- a/llvm/test/Transforms/LICM/loopsink.ll +++ b/llvm/test/Transforms/LICM/loopsink.ll @@ -198,7 +198,7 @@ define i32 @t3(i32, i32) #0 !prof !0 { ; For single-BB loop with <=1 avg trip count, sink load to b1 ; CHECK: t4 ; CHECK: .preheader: -; CHECK-not: load i32, i32* @g +; CHECK-NOT: load i32, i32* @g ; CHECK: .b1: ; CHECK: load i32, i32* @g ; CHECK: .exit: diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/merge-tbaa.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/merge-tbaa.ll index 3c283dc..b4493a8 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/X86/merge-tbaa.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/merge-tbaa.ll @@ -43,4 +43,4 @@ entry: !8 = !{!3, !7, i64 4} ; CHECK-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", {{.*}}, i64 0} -; CHECK-FAG: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0} +; CHECK-DAG: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0} diff --git a/llvm/test/Transforms/LoopInterchange/profitability.ll b/llvm/test/Transforms/LoopInterchange/profitability.ll index ee4b7d5..9fd2174 100644 --- a/llvm/test/Transforms/LoopInterchange/profitability.ll +++ b/llvm/test/Transforms/LoopInterchange/profitability.ll @@ -98,7 +98,7 @@ for.end21: ;; A[i-1][j-1] = A[i - 1][j-1] + B[i][j]; ; CHECK: Name: InterchangeNotProfitable -; CHECK-ENXT: Function: interchange_03 +; CHECK-NEXT: Function: interchange_03 define void @interchange_03(){ entry: br label %for1.header @@ -136,7 +136,7 @@ for.end19: ;; A[i][j] = A[i][j]+k; ; CHECK: Name: InterchangeNotProfitable -; CHECK-ENXT: Function: interchange_04 +; CHECK-NEXT: Function: interchange_04 define void @interchange_04(i32 %k) { entry: br label %for.cond1.preheader diff --git a/llvm/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll b/llvm/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll index 4e7880d..34c6d74 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll @@ -16,7 +16,7 @@ target triple = "x86_64-unknown-linux-gnu" ; widest type in the loop for maximum bandwidth when ; -vectorizer-maximize-bandwidth is indicated. ; -; CHECK-label: foo +; CHECK-LABEL: foo ; CHECK-AVX1: LV: Selecting VF: 16. ; CHECK-AVX2: LV: Selecting VF: 32. define void @foo() { diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll b/llvm/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll index 86899d2..6be0b41 100644 --- a/llvm/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll +++ b/llvm/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll @@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.11.0" declare cc42 double @llvm.experimental.deoptimize.f64(...) define double @caller_3() gc "statepoint-example" { -; CHECK-LABELL @caller_3( +; CHECK-LABEL: @caller_3( ; CHECK: call cc42 token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint ; CHECK: unreachable diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_line_offset.test b/llvm/test/tools/llvm-dwarfdump/X86/debug_line_offset.test index 26a9145..8b8c7bc 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_line_offset.test +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_line_offset.test @@ -3,11 +3,11 @@ RUN: -debug-line=0x0 | FileCheck %s --check-prefix=CHECK-A CHECK-A: debug_line[0x00000000] CHECK-A: Address Line Column File ISA Discriminator Flags -CHECK-A-NET: ------------------ ------ ------ ------ --- ------------- ------------- -CHECK-A-NET: 0x0000000000000000 26 0 1 0 0 is_stmt -CHECK-A-NET: 0x0000000000000004 27 10 1 0 0 is_stmt prologue_end -CHECK-A-NET: 0x0000000000000009 27 3 1 0 0 -CHECK-A-NET: 0x0000000000000074 27 3 1 0 0 end_sequence +CHECK-A-NEXT: ------------------ ------ ------ ------ --- ------------- ------------- +CHECK-A-NEXT: 0x0000000000000000 26 0 1 0 0 is_stmt +CHECK-A-NEXT: 0x0000000000000004 27 10 1 0 0 is_stmt prologue_end +CHECK-A-NEXT: 0x0000000000000009 27 3 1 0 0 +CHECK-A-NEXT: 0x0000000000000074 27 3 1 0 0 end_sequence CHECK-A-NOT: debug_line[0x0000009a] RUN: llvm-dwarfdump %S/../../dsymutil/Inputs/basic-lto-dw4.macho.x86_64.o \ -- 2.7.4