From d9fa8147c4a0d8351f4a2e65803f1f354ca4f56b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 25 Jul 2018 05:22:13 +0000 Subject: [PATCH] [X86] Autogenerate complete checks and fix a failure introduced in r337875. llvm-svn: 337889 --- llvm/test/CodeGen/X86/lea-opt.ll | 235 +++++++++++++++++++++++++++++---------- 1 file changed, 178 insertions(+), 57 deletions(-) diff --git a/llvm/test/CodeGen/X86/lea-opt.ll b/llvm/test/CodeGen/X86/lea-opt.ll index 9e0e34b..b285a4e 100644 --- a/llvm/test/CodeGen/X86/lea-opt.ll +++ b/llvm/test/CodeGen/X86/lea-opt.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED ; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED @@ -8,6 +9,50 @@ @arr2 = external global [65 x %struct.anon2], align 16 define void @test1(i64 %x) nounwind { +; ENABLED-LABEL: test1: +; ENABLED: # %bb.0: # %entry +; ENABLED-NEXT: shlq $2, %rdi +; ENABLED-NEXT: movl arr1(%rdi,%rdi,2), %ecx +; ENABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax +; ENABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %ecx +; ENABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %ecx +; ENABLED-NEXT: cmpl $2, %ecx +; ENABLED-NEXT: je .LBB0_3 +; ENABLED-NEXT: # %bb.1: # %entry +; ENABLED-NEXT: cmpl $1, %ecx +; ENABLED-NEXT: jne .LBB0_4 +; ENABLED-NEXT: # %bb.2: # %sw.bb.1 +; ENABLED-NEXT: movl $111, (%rax) +; ENABLED-NEXT: movl $222, 4(%rax) +; ENABLED-NEXT: retq +; ENABLED-NEXT: .LBB0_3: # %sw.bb.2 +; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC +; ENABLED-NEXT: .LBB0_4: # %sw.epilog +; ENABLED-NEXT: retq +; +; DISABLED-LABEL: test1: +; DISABLED: # %bb.0: # %entry +; DISABLED-NEXT: shlq $2, %rdi +; DISABLED-NEXT: movl arr1(%rdi,%rdi,2), %edx +; DISABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax +; DISABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %edx +; DISABLED-NEXT: leaq arr1+8(%rdi,%rdi,2), %rcx +; DISABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %edx +; DISABLED-NEXT: cmpl $2, %edx +; DISABLED-NEXT: je .LBB0_3 +; DISABLED-NEXT: # %bb.1: # %entry +; DISABLED-NEXT: cmpl $1, %edx +; DISABLED-NEXT: jne .LBB0_4 +; DISABLED-NEXT: # %bb.2: # %sw.bb.1 +; DISABLED-NEXT: movl $111, (%rax) +; DISABLED-NEXT: movl $222, (%rcx) +; DISABLED-NEXT: retq +; DISABLED-NEXT: .LBB0_3: # %sw.bb.2 +; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC +; DISABLED-NEXT: .LBB0_4: # %sw.epilog +; DISABLED-NEXT: retq entry: %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0 %tmp = load i32, i32* %a, align 4 @@ -34,22 +79,53 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void -; CHECK-LABEL: test1: -; CHECK: shlq $2, [[REG1:%[a-z]+]] -; CHECK: movl arr1([[REG1]],[[REG1]],2), {{.*}} -; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]] -; CHECK: subl arr1+4([[REG1]],[[REG1]],2), {{.*}} -; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]] -; CHECK: addl arr1+8([[REG1]],[[REG1]],2), {{.*}} -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } define void @test2(i64 %x) nounwind optsize { +; ENABLED-LABEL: test2: +; ENABLED: # %bb.0: # %entry +; ENABLED-NEXT: shlq $2, %rdi +; ENABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax +; ENABLED-NEXT: movl -4(%rax), %ecx +; ENABLED-NEXT: subl (%rax), %ecx +; ENABLED-NEXT: addl 4(%rax), %ecx +; ENABLED-NEXT: cmpl $2, %ecx +; ENABLED-NEXT: je .LBB1_3 +; ENABLED-NEXT: # %bb.1: # %entry +; ENABLED-NEXT: cmpl $1, %ecx +; ENABLED-NEXT: jne .LBB1_4 +; ENABLED-NEXT: # %bb.2: # %sw.bb.1 +; ENABLED-NEXT: movl $111, (%rax) +; ENABLED-NEXT: movl $222, 4(%rax) +; ENABLED-NEXT: retq +; ENABLED-NEXT: .LBB1_3: # %sw.bb.2 +; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC +; ENABLED-NEXT: .LBB1_4: # %sw.epilog +; ENABLED-NEXT: retq +; +; DISABLED-LABEL: test2: +; DISABLED: # %bb.0: # %entry +; DISABLED-NEXT: shlq $2, %rdi +; DISABLED-NEXT: movl arr1(%rdi,%rdi,2), %edx +; DISABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax +; DISABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %edx +; DISABLED-NEXT: leaq arr1+8(%rdi,%rdi,2), %rcx +; DISABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %edx +; DISABLED-NEXT: cmpl $2, %edx +; DISABLED-NEXT: je .LBB1_3 +; DISABLED-NEXT: # %bb.1: # %entry +; DISABLED-NEXT: cmpl $1, %edx +; DISABLED-NEXT: jne .LBB1_4 +; DISABLED-NEXT: # %bb.2: # %sw.bb.1 +; DISABLED-NEXT: movl $111, (%rax) +; DISABLED-NEXT: movl $222, (%rcx) +; DISABLED-NEXT: retq +; DISABLED-NEXT: .LBB1_3: # %sw.bb.2 +; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC +; DISABLED-NEXT: .LBB1_4: # %sw.epilog +; DISABLED-NEXT: retq entry: %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0 %tmp = load i32, i32* %a, align 4 @@ -76,22 +152,6 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void -; CHECK-LABEL: test2: -; CHECK: shlq $2, [[REG1:%[a-z]+]] -; DISABLED: movl arr1([[REG1]],[[REG1]],2), {{.*}} -; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]] -; ENABLED: movl -4([[REG2]]), {{.*}} -; ENABLED: subl ([[REG2]]), {{.*}} -; ENABLED: addl 4([[REG2]]), {{.*}} -; DISABLED: subl arr1+4([[REG1]],[[REG1]],2), {{.*}} -; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]] -; DISABLED: addl arr1+8([[REG1]],[[REG1]],2), {{.*}} -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } ; Check that LEA optimization pass takes into account a resultant address @@ -99,6 +159,51 @@ sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, ; address recalculation. define void @test3(i64 %x) nounwind optsize { +; ENABLED-LABEL: test3: +; ENABLED: # %bb.0: # %entry +; ENABLED-NEXT: movq %rdi, %rax +; ENABLED-NEXT: shlq $7, %rax +; ENABLED-NEXT: leaq arr2+132(%rax,%rdi,8), %rcx +; ENABLED-NEXT: leaq arr2(%rax,%rdi,8), %rax +; ENABLED-NEXT: movl (%rcx), %edx +; ENABLED-NEXT: addl (%rax), %edx +; ENABLED-NEXT: cmpl $2, %edx +; ENABLED-NEXT: je .LBB2_3 +; ENABLED-NEXT: # %bb.1: # %entry +; ENABLED-NEXT: cmpl $1, %edx +; ENABLED-NEXT: jne .LBB2_4 +; ENABLED-NEXT: # %bb.2: # %sw.bb.1 +; ENABLED-NEXT: movl $111, (%rcx) +; ENABLED-NEXT: movl $222, (%rax) +; ENABLED-NEXT: retq +; ENABLED-NEXT: .LBB2_3: # %sw.bb.2 +; ENABLED-NEXT: movl $333, (%rcx) # imm = 0x14D +; ENABLED-NEXT: movl %eax, (%rax) +; ENABLED-NEXT: .LBB2_4: # %sw.epilog +; ENABLED-NEXT: retq +; +; DISABLED-LABEL: test3: +; DISABLED: # %bb.0: # %entry +; DISABLED-NEXT: movq %rdi, %rsi +; DISABLED-NEXT: shlq $7, %rsi +; DISABLED-NEXT: leaq arr2+132(%rsi,%rdi,8), %rcx +; DISABLED-NEXT: leaq arr2(%rsi,%rdi,8), %rax +; DISABLED-NEXT: movl arr2+132(%rsi,%rdi,8), %edx +; DISABLED-NEXT: addl arr2(%rsi,%rdi,8), %edx +; DISABLED-NEXT: cmpl $2, %edx +; DISABLED-NEXT: je .LBB2_3 +; DISABLED-NEXT: # %bb.1: # %entry +; DISABLED-NEXT: cmpl $1, %edx +; DISABLED-NEXT: jne .LBB2_4 +; DISABLED-NEXT: # %bb.2: # %sw.bb.1 +; DISABLED-NEXT: movl $111, (%rcx) +; DISABLED-NEXT: movl $222, (%rax) +; DISABLED-NEXT: retq +; DISABLED-NEXT: .LBB2_3: # %sw.bb.2 +; DISABLED-NEXT: movl $333, (%rcx) # imm = 0x14D +; DISABLED-NEXT: movl %eax, (%rax) +; DISABLED-NEXT: .LBB2_4: # %sw.epilog +; DISABLED-NEXT: retq entry: %a = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 2 %tmp = load i32, i32* %a, align 4 @@ -124,25 +229,57 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void -; CHECK-LABEL: test3: -; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]] -; CHECK: leaq arr2+132([[REG1]]), [[REG2:%[a-z]+]] -; CHECK: leaq arr2([[REG1]]), [[REG3:%[a-z]+]] ; REG3's definition is closer to movl than REG2's, but the pass still chooses ; REG2 because it provides the resultant address displacement fitting 1 byte. -; ENABLED: movl ([[REG2]]), {{.*}} -; ENABLED: addl ([[REG3]]), {{.*}} -; DISABLED: movl arr2+132([[REG1]]), {{.*}} -; DISABLED: addl arr2([[REG1]]), {{.*}} -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl {{.*}}, ([[REG3]]) } define void @test4(i64 %x) nounwind minsize { +; ENABLED-LABEL: test4: +; ENABLED: # %bb.0: # %entry +; ENABLED-NEXT: imulq $12, %rdi, %rax +; ENABLED-NEXT: leaq arr1+4(%rax), %rax +; ENABLED-NEXT: movl -4(%rax), %ecx +; ENABLED-NEXT: subl (%rax), %ecx +; ENABLED-NEXT: addl 4(%rax), %ecx +; ENABLED-NEXT: cmpl $2, %ecx +; ENABLED-NEXT: je .LBB3_3 +; ENABLED-NEXT: # %bb.1: # %entry +; ENABLED-NEXT: cmpl $1, %ecx +; ENABLED-NEXT: jne .LBB3_4 +; ENABLED-NEXT: # %bb.2: # %sw.bb.1 +; ENABLED-NEXT: movl $111, (%rax) +; ENABLED-NEXT: movl $222, 4(%rax) +; ENABLED-NEXT: retq +; ENABLED-NEXT: .LBB3_3: # %sw.bb.2 +; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC +; ENABLED-NEXT: .LBB3_4: # %sw.epilog +; ENABLED-NEXT: retq +; +; DISABLED-LABEL: test4: +; DISABLED: # %bb.0: # %entry +; DISABLED-NEXT: imulq $12, %rdi, %rsi +; DISABLED-NEXT: movl arr1(%rsi), %edx +; DISABLED-NEXT: leaq arr1+4(%rsi), %rax +; DISABLED-NEXT: subl arr1+4(%rsi), %edx +; DISABLED-NEXT: leaq arr1+8(%rsi), %rcx +; DISABLED-NEXT: addl arr1+8(%rsi), %edx +; DISABLED-NEXT: cmpl $2, %edx +; DISABLED-NEXT: je .LBB3_3 +; DISABLED-NEXT: # %bb.1: # %entry +; DISABLED-NEXT: cmpl $1, %edx +; DISABLED-NEXT: jne .LBB3_4 +; DISABLED-NEXT: # %bb.2: # %sw.bb.1 +; DISABLED-NEXT: movl $111, (%rax) +; DISABLED-NEXT: movl $222, (%rcx) +; DISABLED-NEXT: retq +; DISABLED-NEXT: .LBB3_3: # %sw.bb.2 +; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D +; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC +; DISABLED-NEXT: .LBB3_4: # %sw.epilog +; DISABLED-NEXT: retq entry: %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0 %tmp = load i32, i32* %a, align 4 @@ -169,20 +306,4 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void -; CHECK-LABEL: test4: -; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]] -; DISABLED: movl arr1([[REG1]]), {{.*}} -; CHECK: leaq arr1+4([[REG1]]), [[REG2:%[a-z]+]] -; ENABLED: movl -4([[REG2]]), {{.*}} -; ENABLED: subl ([[REG2]]), {{.*}} -; ENABLED: addl 4([[REG2]]), {{.*}} -; DISABLED: subl arr1+4([[REG1]]), {{.*}} -; DISABLED: leaq arr1+8([[REG1]]), [[REG3:%[a-z]+]] -; DISABLED: addl arr1+8([[REG1]]), {{.*}} -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) -; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) -; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } -- 2.7.4