From d9e4c1044072c550bcdb04e2888d85a3f670776f Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 17 Feb 2023 14:29:21 -0800 Subject: [PATCH] [AArch64] Simplify with MCSubtargetInfo::hasFeature. NFC --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 5 ++--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 3 +-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index c110a04..8393fb1 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3408,8 +3408,7 @@ AArch64AsmParser::parseCondCodeString(StringRef Cond, std::string &Suggestion) { .Case("nv", AArch64CC::NV) .Default(AArch64CC::Invalid); - if (CC == AArch64CC::Invalid && - getSTI().getFeatureBits()[AArch64::FeatureSVE]) { + if (CC == AArch64CC::Invalid && getSTI().hasFeature(AArch64::FeatureSVE)) { CC = StringSwitch(Cond.lower()) .Case("none", AArch64CC::EQ) .Case("any", AArch64CC::NE) @@ -6355,7 +6354,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // instruction for FP registers correctly in some rare circumstances. Convert // it to a safe instruction and warn (because silently changing someone's // assembly is rude). - if (getSTI().getFeatureBits()[AArch64::FeatureZCZeroingFPWorkaround] && + if (getSTI().hasFeature(AArch64::FeatureZCZeroingFPWorkaround) && NumOperands == 4 && Tok == "movi") { AArch64Operand &Op1 = static_cast(*Operands[1]); AArch64Operand &Op2 = static_cast(*Operands[2]); diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 6ff5459..088e1a6 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -213,8 +213,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, int ImmS = MI->getOperand(4).getImm(); if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && - (ImmR == 0 || ImmS < ImmR) && - STI.getFeatureBits()[AArch64::HasV8_2aOps]) { + (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) { // BFC takes precedence over its entire range, sligtly differently to BFI. int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; int LSB = (BitWidth - ImmR) % BitWidth; -- 2.7.4