From d9004dfbabc62887f09775297436792077ce4496 Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Fri, 8 Apr 2022 03:24:46 -0400 Subject: [PATCH] [PowerPC] mapping hardward loop intrinsics to powerpc pseudo Map hardware loop intrinsics loop_decrement and set_loop_iteration to the new PowerPC pseudo instructions, so that the hardware loop intrinsics will be expanded to normal cmp+branch form or ctrloop form based on the CTR register usage on MIR level. Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D123366 --- llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 31 +++++------- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 56 ++++++++++++++++++++++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 50 -------------------- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 10 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 9 ++-- llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll | 36 +++++++++----- llvm/test/CodeGen/PowerPC/ctrloops32.mir | 70 ++++++++++++++-------------- llvm/test/CodeGen/PowerPC/ctrloops64.mir | 70 ++++++++++++++-------------- llvm/test/CodeGen/PowerPC/sms-phi.ll | 8 ++-- 9 files changed, 172 insertions(+), 168 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index 48167c3..cb0519c 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -7,21 +7,21 @@ //===----------------------------------------------------------------------===// // // This pass generates machine instructions for the CTR loops related pseudos: -// 1: MTCTRPseudo/DecreaseCTRPseudo -// 2: MTCTR8Pseudo/DecreaseCTR8Pseudo +// 1: MTCTRloop/DecreaseCTRloop +// 2: MTCTR8loop/DecreaseCTR8loop // // If a CTR loop can be generated: -// 1: MTCTRPseudo/MTCTR8Pseudo will be converted to "mtctr" -// 2: DecreaseCTRPseudo/DecreaseCTR8Pseudo will be converted to "bdnz/bdz" and +// 1: MTCTRloop/MTCTR8loop will be converted to "mtctr" +// 2: DecreaseCTRloop/DecreaseCTR8loop will be converted to "bdnz/bdz" and // its user branch instruction can be deleted. // // If a CTR loop can not be generated due to clobber of CTR: -// 1: MTCTRPseudo/MTCTR8Pseudo can be deleted. -// 2: DecreaseCTRPseudo/DecreaseCTR8Pseudo will be converted to "addi -1" and +// 1: MTCTRloop/MTCTR8loop can be deleted. +// 2: DecreaseCTRloop/DecreaseCTR8loop will be converted to "addi -1" and // a "cmplwi/cmpldi". // // This pass runs just before register allocation, because we don't want -// register allocator to allocate register for DecreaseCTRPseudo if a CTR can be +// register allocator to allocate register for DecreaseCTRloop if a CTR can be // generated or if a CTR loop can not be generated, we don't have any condition // register for the new added "cmplwi/cmpldi". // @@ -148,8 +148,8 @@ bool PPCCTRLoops::processLoop(MachineLoop *ML) { return true; auto IsLoopStart = [](MachineInstr &MI) { - return MI.getOpcode() == PPC::MTCTRPseudo || - MI.getOpcode() == PPC::MTCTR8Pseudo; + return MI.getOpcode() == PPC::MTCTRloop || + MI.getOpcode() == PPC::MTCTR8loop; }; auto SearchForStart = @@ -166,7 +166,7 @@ bool PPCCTRLoops::processLoop(MachineLoop *ML) { bool InvalidCTRLoop = false; MachineBasicBlock *Preheader = ML->getLoopPreheader(); - // If there is no preheader for this loop, there must be no MTCTRPseudo + // If there is no preheader for this loop, there must be no MTCTRloop // either. if (!Preheader) return false; @@ -205,8 +205,8 @@ bool PPCCTRLoops::processLoop(MachineLoop *ML) { // normal loop. for (auto *MBB : reverse(ML->getBlocks())) { for (auto &MI : *MBB) { - if (MI.getOpcode() == PPC::DecreaseCTRPseudo || - MI.getOpcode() == PPC::DecreaseCTR8Pseudo) + if (MI.getOpcode() == PPC::DecreaseCTRloop || + MI.getOpcode() == PPC::DecreaseCTR8loop) Dec = &MI; else if (!InvalidCTRLoop) // If any instruction clobber CTR, then we can not generate a CTR loop. @@ -341,18 +341,11 @@ void PPCCTRLoops::expandCTRLoops(MachineLoop *ML, MachineInstr *Start, llvm_unreachable("Unhandled branch user for DecreaseCTRloop."); } - unsigned MTCTROpcode = Is64Bit ? PPC::MTCTR8 : PPC::MTCTR; - - // Generate "mtctr" in the loop preheader. - BuildMI(*Preheader, Start, Start->getDebugLoc(), TII->get(MTCTROpcode)) - .addReg(Start->getOperand(0).getReg()); - // Generate "bdnz/bdz" in the exiting block just before the terminator. BuildMI(*Exiting, &*BrInstr, BrInstr->getDebugLoc(), TII->get(Opcode)) .addMBB(BrInstr->getOperand(1).getMBB()); // Remove the pseudo instructions. - Start->eraseFromParent(); BrInstr->eraseFromParent(); Dec->eraseFromParent(); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index e1264d9..4ce36e8 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -417,6 +417,7 @@ namespace { private: bool trySETCC(SDNode *N); bool tryFoldSWTestBRCC(SDNode *N); + bool trySelectLoopCountIntrinsic(SDNode *N); bool tryAsSingleRLDICL(SDNode *N); bool tryAsSingleRLDICR(SDNode *N); bool tryAsSingleRLWINM(SDNode *N); @@ -4718,6 +4719,59 @@ bool PPCDAGToDAGISel::tryFoldSWTestBRCC(SDNode *N) { return false; } +bool PPCDAGToDAGISel::trySelectLoopCountIntrinsic(SDNode *N) { + // Sometimes the promoted value of the intrinsic is ANDed by some non-zero + // value, for example when crbits is disabled. If so, select the + // loop_decrement intrinsics now. + ISD::CondCode CC = cast(N->getOperand(1))->get(); + SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); + + if (LHS.getOpcode() != ISD::AND || !isa(LHS.getOperand(1)) || + isNullConstant(LHS.getOperand(1))) + return false; + + if (LHS.getOperand(0).getOpcode() != ISD::INTRINSIC_W_CHAIN || + cast(LHS.getOperand(0).getOperand(1))->getZExtValue() != + Intrinsic::loop_decrement) + return false; + + if (!isa(RHS)) + return false; + + assert((CC == ISD::SETEQ || CC == ISD::SETNE) && + "Counter decrement comparison is not EQ or NE"); + + SDValue OldDecrement = LHS.getOperand(0); + assert(OldDecrement.hasOneUse() && "loop decrement has more than one use!"); + + SDLoc DecrementLoc(OldDecrement); + SDValue ChainInput = OldDecrement.getOperand(0); + SDValue DecrementOps[] = {Subtarget->isPPC64() ? getI64Imm(1, DecrementLoc) + : getI32Imm(1, DecrementLoc)}; + unsigned DecrementOpcode = + Subtarget->isPPC64() ? PPC::DecreaseCTR8loop : PPC::DecreaseCTRloop; + SDNode *NewDecrement = CurDAG->getMachineNode(DecrementOpcode, DecrementLoc, + MVT::i1, DecrementOps); + + unsigned Val = cast(RHS)->getZExtValue(); + bool IsBranchOnTrue = (CC == ISD::SETEQ && Val) || (CC == ISD::SETNE && !Val); + unsigned Opcode = IsBranchOnTrue ? PPC::BC : PPC::BCn; + + ReplaceUses(LHS.getValue(0), LHS.getOperand(1)); + CurDAG->RemoveDeadNode(LHS.getNode()); + + // Mark the old loop_decrement intrinsic as dead. + ReplaceUses(OldDecrement.getValue(1), ChainInput); + CurDAG->RemoveDeadNode(OldDecrement.getNode()); + + SDValue Chain = CurDAG->getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, + ChainInput, N->getOperand(0)); + + CurDAG->SelectNodeTo(N, Opcode, MVT::Other, SDValue(NewDecrement, 0), + N->getOperand(4), Chain); + return true; +} + bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) { assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected"); unsigned Imm; @@ -5739,6 +5793,8 @@ void PPCDAGToDAGISel::Select(SDNode *N) { case ISD::BR_CC: { if (tryFoldSWTestBRCC(N)) return; + if (trySelectLoopCountIntrinsic(N)) + return; ISD::CondCode CC = cast(N->getOperand(1))->get(); unsigned PCC = getPredicateForSetCC(CC, N->getOperand(2).getValueType(), Subtarget); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 8961b05..8e0633f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15719,25 +15719,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, return SDValue(VCMPrecNode, 0); } break; - case ISD::BRCOND: { - SDValue Cond = N->getOperand(1); - SDValue Target = N->getOperand(2); - - if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN && - cast(Cond.getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement) { - - // We now need to make the intrinsic dead (it cannot be instruction - // selected). - DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0)); - assert(Cond.getNode()->hasOneUse() && - "Counter decrement has more than one use"); - - return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, - N->getOperand(0), Target); - } - } - break; case ISD::BR_CC: { // If this is a branch on an altivec predicate comparison, lower this so // that we don't have to do a MFOCRF: instead, branch directly on CR6. This @@ -15746,37 +15727,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, ISD::CondCode CC = cast(N->getOperand(1))->get(); SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); - // Sometimes the promoted value of the intrinsic is ANDed by some non-zero - // value. If so, pass-through the AND to get to the intrinsic. - if (LHS.getOpcode() == ISD::AND && - LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN && - cast(LHS.getOperand(0).getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement && - isa(LHS.getOperand(1)) && - !isNullConstant(LHS.getOperand(1))) - LHS = LHS.getOperand(0); - - if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN && - cast(LHS.getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement && - isa(RHS)) { - assert((CC == ISD::SETEQ || CC == ISD::SETNE) && - "Counter decrement comparison is not EQ or NE"); - - unsigned Val = cast(RHS)->getZExtValue(); - bool isBDNZ = (CC == ISD::SETEQ && Val) || - (CC == ISD::SETNE && !Val); - - // We now need to make the intrinsic dead (it cannot be instruction - // selected). - DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0)); - assert(LHS.getNode()->hasOneUse() && - "Counter decrement has more than one use"); - - return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, - N->getOperand(0), N->getOperand(4)); - } - int CompareOpc; bool isDot; diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index dbe7a78..7d648b1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -580,13 +580,9 @@ def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), PPC970_DGroup_First, PPC970_Unit_FXU; } - -let hasSideEffects = 1, Defs = [CTR8] in -def MTCTR8Pseudo : PPCEmitTimePseudo<(outs), (ins g8rc:$rS), "#MTCTR8Pseudo", []>; - -let hasSideEffects = 1, Uses = [CTR8], Defs = [CTR8] in -def DecreaseCTR8Pseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), - "#DecreaseCTR8Pseudo", []>; +let hasSideEffects = 1, hasNoSchedulingInfo = 1, Uses = [CTR8], Defs = [CTR8] in +def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), + "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; let Pattern = [(set i64:$rT, readcyclecounter)] in def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 88d3290..212a0e0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -2549,12 +2549,9 @@ def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), PPC970_DGroup_First, PPC970_Unit_FXU; } -let hasSideEffects = 1, Defs = [CTR] in -def MTCTRPseudo : PPCEmitTimePseudo<(outs), (ins gprc:$rS), "#MTCTRPseudo", []>; - -let hasSideEffects = 1, Uses = [CTR], Defs = [CTR] in -def DecreaseCTRPseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), - "#DecreaseCTRPseudo", []>; +let hasSideEffects = 1, hasNoSchedulingInfo = 1, Uses = [CTR], Defs = [CTR] in +def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), + "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; let hasSideEffects = 0 in { let Defs = [LR] in { diff --git a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll index 39f33d9..9890830 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll +++ b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll @@ -29,7 +29,8 @@ define void @test1(i32 %c) nounwind { ; AIX64-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtoc]] :: (volatile dereferenceable load (s32) from @a) ; AIX64-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]] ; AIX64-NEXT: STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a) - ; AIX64-NEXT: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1 ; AIX64-NEXT: B %bb.2 ; AIX64-NEXT: {{ $}} ; AIX64-NEXT: bb.2.for.end: @@ -50,7 +51,8 @@ define void @test1(i32 %c) nounwind { ; AIX32-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LWZtoc]] :: (volatile dereferenceable load (s32) from @a) ; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY]] ; AIX32-NEXT: STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a) - ; AIX32-NEXT: BDNZ %bb.1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: BC killed [[DecreaseCTRloop]], %bb.1 ; AIX32-NEXT: B %bb.2 ; AIX32-NEXT: {{ $}} ; AIX32-NEXT: bb.2.for.end: @@ -73,7 +75,8 @@ define void @test1(i32 %c) nounwind { ; LE64-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtocL]] :: (volatile dereferenceable load (s32) from @a) ; LE64-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]] ; LE64-NEXT: STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a) - ; LE64-NEXT: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1 ; LE64-NEXT: B %bb.2 ; LE64-NEXT: {{ $}} ; LE64-NEXT: bb.2.for.end: @@ -125,7 +128,8 @@ define void @test2(i32 %c, i32 %d) nounwind { ; AIX64-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtoc]] :: (volatile dereferenceable load (s32) from @a) ; AIX64-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY2]] ; AIX64-NEXT: STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a) - ; AIX64-NEXT: BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.2 ; AIX64-NEXT: B %bb.3 ; AIX64-NEXT: {{ $}} ; AIX64-NEXT: bb.3.for.end: @@ -153,7 +157,8 @@ define void @test2(i32 %c, i32 %d) nounwind { ; AIX32-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LWZtoc]] :: (volatile dereferenceable load (s32) from @a) ; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]] ; AIX32-NEXT: STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a) - ; AIX32-NEXT: BDNZ %bb.2, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: BC killed [[DecreaseCTRloop]], %bb.2 ; AIX32-NEXT: B %bb.3 ; AIX32-NEXT: {{ $}} ; AIX32-NEXT: bb.3.for.end: @@ -189,7 +194,8 @@ define void @test2(i32 %c, i32 %d) nounwind { ; LE64-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtocL]] :: (volatile dereferenceable load (s32) from @a) ; LE64-NEXT: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY2]] ; LE64-NEXT: STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a) - ; LE64-NEXT: BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.2 ; LE64-NEXT: B %bb.3 ; LE64-NEXT: {{ $}} ; LE64-NEXT: bb.3.for.end: @@ -245,7 +251,8 @@ define void @test3(i32 %c, i32 %d) nounwind { ; AIX64-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]] ; AIX64-NEXT: STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a) ; AIX64-NEXT: [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY2]] - ; AIX64-NEXT: BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.2 ; AIX64-NEXT: B %bb.3 ; AIX64-NEXT: {{ $}} ; AIX64-NEXT: bb.3.for.end: @@ -276,7 +283,8 @@ define void @test3(i32 %c, i32 %d) nounwind { ; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]] ; AIX32-NEXT: STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a) ; AIX32-NEXT: [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY1]] - ; AIX32-NEXT: BDNZ %bb.2, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: BC killed [[DecreaseCTRloop]], %bb.2 ; AIX32-NEXT: B %bb.3 ; AIX32-NEXT: {{ $}} ; AIX32-NEXT: bb.3.for.end: @@ -315,7 +323,8 @@ define void @test3(i32 %c, i32 %d) nounwind { ; LE64-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]] ; LE64-NEXT: STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a) ; LE64-NEXT: [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY2]] - ; LE64-NEXT: BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.2 ; LE64-NEXT: B %bb.3 ; LE64-NEXT: {{ $}} ; LE64-NEXT: bb.3.for.end: @@ -361,7 +370,8 @@ define i32 @test4(i32 %inp) { ; AIX64-NEXT: bb.1.for.body: ; AIX64-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; AIX64-NEXT: {{ $}} - ; AIX64-NEXT: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; AIX64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1 ; AIX64-NEXT: B %bb.2 ; AIX64-NEXT: {{ $}} ; AIX64-NEXT: bb.2.return: @@ -390,7 +400,8 @@ define i32 @test4(i32 %inp) { ; AIX32-NEXT: bb.1.for.body: ; AIX32-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; AIX32-NEXT: {{ $}} - ; AIX32-NEXT: BDNZ %bb.1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr + ; AIX32-NEXT: BC killed [[DecreaseCTRloop]], %bb.1 ; AIX32-NEXT: B %bb.2 ; AIX32-NEXT: {{ $}} ; AIX32-NEXT: bb.2.return: @@ -420,7 +431,8 @@ define i32 @test4(i32 %inp) { ; LE64-NEXT: bb.1.for.body: ; LE64-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; LE64-NEXT: {{ $}} - ; LE64-NEXT: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 + ; LE64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1 ; LE64-NEXT: B %bb.2 ; LE64-NEXT: {{ $}} ; LE64-NEXT: bb.2.return: diff --git a/llvm/test/CodeGen/PowerPC/ctrloops32.mir b/llvm/test/CodeGen/PowerPC/ctrloops32.mir index 90ee800..ffe62cf 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloops32.mir +++ b/llvm/test/CodeGen/PowerPC/ctrloops32.mir @@ -10,16 +10,16 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK: MTCTR + ; CHECK: MTCTRloop ; CHECK: BDNZ ; CHECK-NOT: ADDI ; CHECK-NOT: CMPLWI ; CHECK-NOT: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -35,17 +35,17 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -61,17 +61,17 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: %1:gprc = MFCTR implicit $ctr - %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -92,12 +92,12 @@ body: | ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr BL @test_fail_use_in_loop, csr_aix32, implicit-def dead $lr, implicit $rm bb.1: - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -119,11 +119,11 @@ body: | ; CHECK-NOT: ADDI ; CHECK-NOT: CMPLWI ; CHECK-NOT: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -144,12 +144,12 @@ body: | ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: BL @test_fail_use_in_loop, csr_aix32, implicit-def dead $lr, implicit $rm - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -174,12 +174,12 @@ body: | renamable %1:crrc = CMPLW killed renamable $r3, killed renamable $r4 renamable %2:crbitrc = COPY %1.sub_gt MTLR %0:gprc, implicit-def $lr - MTCTRPseudo %0:gprc, implicit-def dead $ctr + MTCTRloop %0:gprc, implicit-def dead $ctr bb.1: BCLRL renamable %2, implicit $lr, implicit $rm - %3:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %3:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %3:crbitrc, %bb.1 B %bb.2 @@ -196,16 +196,16 @@ body: | liveins: $ctr %0:gprc = LI 2048 - ; CHECK-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -222,16 +222,16 @@ body: | INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr %0:gprc = LI 2048 - ; CHECK2-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: - %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -248,16 +248,16 @@ body: | %0:gprc = MFCTR implicit $ctr %1:gprc = LI 2048 - ; CHECK: MTCTR + ; CHECK: MTCTRloop ; CHECK: BDNZ ; CHECK-NOT: ADDI ; CHECK-NOT: CMPLWI ; CHECK-NOT: BC - MTCTRPseudo killed %1:gprc, implicit-def dead $ctr + MTCTRloop killed %1:gprc, implicit-def dead $ctr bb.1: - %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -273,17 +273,17 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr %1:gprc = MFCTR implicit $ctr bb.1: - %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -299,17 +299,17 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK-NOT: MTCTR + ; CHECK-NOT: MTCTRloop ; CHECK-NOT: BDNZ ; CHECK: ADDI ; CHECK: CMPLWI ; CHECK: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr bb.1: - %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -325,16 +325,16 @@ body: | bb.0.entry: %0:gprc = LI 2048 - ; CHECK: MTCTR + ; CHECK: MTCTRloop ; CHECK: BDNZ ; CHECK-NOT: ADDI ; CHECK-NOT: CMPLWI ; CHECK-NOT: BC - MTCTRPseudo killed %0:gprc, implicit-def dead $ctr + MTCTRloop killed %0:gprc, implicit-def dead $ctr bb.1: - %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr + %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr BC killed %2:crbitrc, %bb.1 B %bb.2 diff --git a/llvm/test/CodeGen/PowerPC/ctrloops64.mir b/llvm/test/CodeGen/PowerPC/ctrloops64.mir index 1d4ed84..8e50c55 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloops64.mir +++ b/llvm/test/CodeGen/PowerPC/ctrloops64.mir @@ -12,16 +12,16 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK: MTCTR8 + ; CHECK: MTCTR8loop ; CHECK: BDNZ8 ; CHECK-NOT: ADDI8 ; CHECK-NOT: CMPLDI ; CHECK-NOT: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -37,17 +37,17 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8 - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -63,17 +63,17 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: %1:g8rc = MFCTR8 implicit $ctr8 - %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -94,12 +94,12 @@ body: | ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 BL8 @test_fail_use_in_loop, csr_ppc64, implicit-def dead $lr8, implicit $rm bb.1: - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -121,11 +121,11 @@ body: | ; CHECK-NOT: ADDI8 ; CHECK-NOT: CMPLDI ; CHECK-NOT: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -146,12 +146,12 @@ body: | ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: BL8 @test_fail_use_in_loop, csr_ppc64, implicit-def dead $lr8, implicit $rm - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -176,12 +176,12 @@ body: | renamable %1:crrc = CMPLD killed renamable $x3, killed renamable $x4 renamable %2:crbitrc = COPY %1.sub_gt MTLR8 %0:g8rc, implicit-def $lr8 - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: BCLRL renamable %2, implicit $lr, implicit $rm - %3:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %3:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %3:crbitrc, %bb.1 B %bb.2 @@ -198,16 +198,16 @@ body: | liveins: $ctr8 %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -224,16 +224,16 @@ body: | INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8 %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: - %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %1:crbitrc, %bb.1 B %bb.2 @@ -250,16 +250,16 @@ body: | %0:g8rc = MFCTR8 implicit $ctr8 %1:g8rc = LI8 2048 - ; CHECK: MTCTR8 + ; CHECK: MTCTR8loop ; CHECK: BDNZ8 ; CHECK-NOT: ADDI8 ; CHECK-NOT: CMPLDI ; CHECK-NOT: BC - MTCTR8Pseudo killed %1:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %1:g8rc, implicit-def dead $ctr8 bb.1: - %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -275,17 +275,17 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 %1:g8rc = MFCTR8 implicit $ctr8 bb.1: - %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -301,17 +301,17 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK-NOT: MTCTR8 + ; CHECK-NOT: MTCTR8loop ; CHECK-NOT: BDNZ8 ; CHECK: ADDI8 ; CHECK: CMPLDI ; CHECK: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8 bb.1: - %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %2:crbitrc, %bb.1 B %bb.2 @@ -327,16 +327,16 @@ body: | bb.0.entry: %0:g8rc = LI8 2048 - ; CHECK: MTCTR8 + ; CHECK: MTCTR8loop ; CHECK: BDNZ8 ; CHECK-NOT: ADDI8 ; CHECK-NOT: CMPLDI ; CHECK-NOT: BC - MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8 + MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8 bb.1: - %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8 + %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8 BC killed %2:crbitrc, %bb.1 B %bb.2 diff --git a/llvm/test/CodeGen/PowerPC/sms-phi.ll b/llvm/test/CodeGen/PowerPC/sms-phi.ll index 3ddf781..4e9031b 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi.ll @@ -4,11 +4,11 @@ ; RUN: >/dev/null | FileCheck %s define dso_local void @sha512() #0 { ;CHECK: prolog: -;CHECK: %18:g8rc = ADD8 %24:g8rc, %23:g8rc +;CHECK: %{{[0-9]+}}:g8rc = ADD8 %{{[0-9]+}}:g8rc, %{{[0-9]+}}:g8rc ;CHECK: epilog: -;CHECK: %28:g8rc_and_g8rc_nox0 = PHI %6:g8rc_and_g8rc_nox0, %bb.3, %22:g8rc_and_g8rc_nox0, %bb.4 -;CHECK-NEXT: %29:g8rc = PHI %12:g8rc, %bb.3, %16:g8rc, %bb.4 -;CHECK-NEXT: %30:g8rc = PHI %15:g8rc, %bb.3, %19:g8rc, %bb.4 +;CHECK: %{{[0-9]+}}:g8rc_and_g8rc_nox0 = PHI %{{[0-9]+}}:g8rc_and_g8rc_nox0, %bb.3, %{{[0-9]+}}:g8rc_and_g8rc_nox0, %bb.4 +;CHECK-NEXT: %{{[0-9]+}}:g8rc = PHI %{{[0-9]+}}:g8rc, %bb.3, %{{[0-9]+}}:g8rc, %bb.4 +;CHECK-NEXT: %{{[0-9]+}}:g8rc = PHI %{{[0-9]+}}:g8rc, %bb.3, %{{[0-9]+}}:g8rc, %bb.4 br label %1 1: ; preds = %1, %0 -- 2.7.4