From d8d8b4574ab40e319d4a32a9c37eae771c43b8f0 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 19 Jul 2021 04:18:27 -0700 Subject: [PATCH] [SLP]Fix possible crash on unreachable incoming values sorting. The incoming values for PHI nodes may come from unreachable BasicBlocks, need to handle this case. Differential Revision: https://reviews.llvm.org/D106264 --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +++-- .../Transforms/SLPVectorizer/X86/unreachable.ll | 26 ++++++++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index b88e5bb..9a4c458 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -8440,8 +8440,10 @@ bool SLPVectorizerPass::vectorizeChainsInBlock(BasicBlock *BB, BoUpSLP &R) { if (auto *I2 = dyn_cast(Opcodes2[I])) { DomTreeNodeBase *NodeI1 = DT->getNode(I1->getParent()); DomTreeNodeBase *NodeI2 = DT->getNode(I2->getParent()); - assert(NodeI1 && "Should only process reachable instructions"); - assert(NodeI2 && "Should only process reachable instructions"); + if (!NodeI1) + return NodeI2 != nullptr; + if (!NodeI2) + return false; assert((NodeI1 == NodeI2) == (NodeI1->getDFSNumIn() == NodeI2->getDFSNumIn()) && "Different nodes should have different DFS numbers"); diff --git a/llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll b/llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll index a4793ce..eed47e6 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll @@ -62,3 +62,29 @@ bb2: ret void } +define void @bar() { +; CHECK-LABEL: @bar( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP:%.*]] = load atomic i8*, i8** undef unordered, align 8 +; CHECK-NEXT: br label [[BB6:%.*]] +; CHECK: bb5: +; CHECK-NEXT: [[TMP4:%.*]] = load atomic i8*, i8** undef unordered, align 8 +; CHECK-NEXT: br label [[BB6]] +; CHECK: bb6: +; CHECK-NEXT: [[TMP7:%.*]] = phi i8* [ [[TMP]], [[BB5:%.*]] ], [ undef, [[BB:%.*]] ] +; CHECK-NEXT: [[TMP8:%.*]] = phi i8* [ [[TMP4]], [[BB5]] ], [ undef, [[BB]] ] +; CHECK-NEXT: ret void +; +bb: + %tmp = load atomic i8*, i8** undef unordered, align 8 + br label %bb6 + +bb5: ; No predecessors! + %tmp4 = load atomic i8*, i8** undef unordered, align 8 + br label %bb6 + +bb6: ; preds = %bb5, %bb + %tmp7 = phi i8* [ %tmp, %bb5 ], [ undef, %bb ] + %tmp8 = phi i8* [ %tmp4, %bb5 ], [ undef, %bb ] + ret void +} -- 2.7.4