From d8b780dcd6574fb2bb71ca4b037fb9ff90b14505 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 20 Jun 2018 13:56:09 +0000 Subject: [PATCH] [Hexagon] Remove 'T' from HasVNN predicates, NFC Patch by Sumanth Gundapaneni. llvm-svn: 335124 --- llvm/lib/Target/Hexagon/HexagonDepArch.td | 12 +- llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 230 ++++++++++----------- llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 16 +- llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td | 2 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td | 2 +- .../Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td | 154 +++++++------- llvm/lib/Target/Hexagon/HexagonPatterns.td | 32 +-- llvm/lib/Target/Hexagon/HexagonPatternsHVX.td | 2 +- llvm/lib/Target/Hexagon/HexagonPseudo.td | 24 +-- llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 10 +- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 20 +- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 4 +- 14 files changed, 258 insertions(+), 258 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.td b/llvm/lib/Target/Hexagon/HexagonDepArch.td index 87dcd96..3594379 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.td +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -11,14 +11,14 @@ def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">; -def HasV65T : Predicate<"HST->hasV65TOps()">, AssemblerPredicate<"ArchV65">; +def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<"ArchV65">; def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">; -def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">; +def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<"ArchV62">; def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">; -def HasV60T : Predicate<"HST->hasV60TOps()">, AssemblerPredicate<"ArchV60">; +def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">; def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">; -def HasV55T : Predicate<"HST->hasV55TOps()">, AssemblerPredicate<"ArchV55">; +def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">; def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "Hexagon::ArchEnum::V4", "Enable Hexagon V4 architecture">; -def HasV4T : Predicate<"HST->hasV4TOps()">, AssemblerPredicate<"ArchV4">; +def HasV4 : Predicate<"HST->hasV4Ops()">, AssemblerPredicate<"ArchV4">; def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">; -def HasV5T : Predicate<"HST->hasV5TOps()">, AssemblerPredicate<"ArchV5">; +def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<"ArchV5">; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index 5256203..b6824fa 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -991,7 +991,7 @@ def A2_roundsat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = round($Rss32):sat", -tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -3301,7 +3301,7 @@ def A5_ACS : HInst< (outs DoubleRegs:$Rxx32, PredRegs:$Pe4), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", -tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55T]> { +tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -3314,7 +3314,7 @@ def A5_vaddhubs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vaddhub($Rss32,$Rtt32):sat", -tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -3327,7 +3327,7 @@ def A6_vcmpbeq_notany : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", -tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65T]> { +tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3336,7 +3336,7 @@ def A6_vminub_RdP : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Pe4), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", -tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> { +tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -4059,7 +4059,7 @@ def F2_conv_d2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_d2df($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4069,7 +4069,7 @@ def F2_conv_d2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_d2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -4081,7 +4081,7 @@ def F2_conv_df2d : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4091,7 +4091,7 @@ def F2_conv_df2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4101,7 +4101,7 @@ def F2_conv_df2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -4113,7 +4113,7 @@ def F2_conv_df2ud : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4123,7 +4123,7 @@ def F2_conv_df2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4133,7 +4133,7 @@ def F2_conv_df2uw : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -4145,7 +4145,7 @@ def F2_conv_df2uw_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000101; let hasNewValue = 1; @@ -4157,7 +4157,7 @@ def F2_conv_df2w : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -4169,7 +4169,7 @@ def F2_conv_df2w_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -4181,7 +4181,7 @@ def F2_conv_sf2d : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4191,7 +4191,7 @@ def F2_conv_sf2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4201,7 +4201,7 @@ def F2_conv_sf2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4211,7 +4211,7 @@ def F2_conv_sf2ud : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4221,7 +4221,7 @@ def F2_conv_sf2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4231,7 +4231,7 @@ def F2_conv_sf2uw : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4243,7 +4243,7 @@ def F2_conv_sf2uw_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4255,7 +4255,7 @@ def F2_conv_sf2w : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4267,7 +4267,7 @@ def F2_conv_sf2w_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4279,7 +4279,7 @@ def F2_conv_ud2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_ud2df($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4289,7 +4289,7 @@ def F2_conv_ud2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_ud2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000001; let hasNewValue = 1; @@ -4301,7 +4301,7 @@ def F2_conv_uw2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_uw2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4311,7 +4311,7 @@ def F2_conv_uw2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_uw2sf($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011001; let hasNewValue = 1; @@ -4323,7 +4323,7 @@ def F2_conv_w2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_w2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4333,7 +4333,7 @@ def F2_conv_w2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_w2sf($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011010; let hasNewValue = 1; @@ -4345,7 +4345,7 @@ def F2_dfclass : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Pd4 = dfclass($Rss32,#$Ii)", -tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> { +tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5]> { let Inst{4-2} = 0b100; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b11011100100; @@ -4356,7 +4356,7 @@ def F2_dfcmpeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4368,7 +4368,7 @@ def F2_dfcmpge : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4380,7 +4380,7 @@ def F2_dfcmpgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4392,7 +4392,7 @@ def F2_dfcmpuo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4404,7 +4404,7 @@ def F2_dfimm_n : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):neg", -tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100101; let prefersSlot3 = 1; @@ -4413,7 +4413,7 @@ def F2_dfimm_p : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):pos", -tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100100; let prefersSlot3 = 1; @@ -4422,7 +4422,7 @@ def F2_sfadd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfadd($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4436,7 +4436,7 @@ def F2_sfclass : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = sfclass($Rs32,#$Ii)", -tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> { +tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101111; @@ -4447,7 +4447,7 @@ def F2_sfcmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.eq($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4459,7 +4459,7 @@ def F2_sfcmpge : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.ge($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4471,7 +4471,7 @@ def F2_sfcmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.gt($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4483,7 +4483,7 @@ def F2_sfcmpuo : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.uo($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4495,7 +4495,7 @@ def F2_sffixupd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupd($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4507,7 +4507,7 @@ def F2_sffixupn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupn($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4519,7 +4519,7 @@ def F2_sffixupr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sffixupr($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011101; let hasNewValue = 1; @@ -4530,7 +4530,7 @@ def F2_sffma : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32)", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4544,7 +4544,7 @@ def F2_sffma_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32):lib", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4558,7 +4558,7 @@ def F2_sffma_sc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", -tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5T]> { +tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -4572,7 +4572,7 @@ def F2_sffms : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32)", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4586,7 +4586,7 @@ def F2_sffms_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32):lib", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4600,7 +4600,7 @@ def F2_sfimm_n : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):neg", -tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011001; let hasNewValue = 1; @@ -4611,7 +4611,7 @@ def F2_sfimm_p : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):pos", -tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011000; let hasNewValue = 1; @@ -4622,7 +4622,7 @@ def F2_sfinvsqrta : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32), "$Rd32,$Pe4 = sfinvsqrta($Rs32)", -tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5T]> { +tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5]> { let Inst{13-7} = 0b0000000; let Inst{31-21} = 0b10001011111; let hasNewValue = 1; @@ -4634,7 +4634,7 @@ def F2_sfmax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmax($Rs32,$Rt32)", -tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4648,7 +4648,7 @@ def F2_sfmin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmin($Rs32,$Rt32)", -tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4662,7 +4662,7 @@ def F2_sfmpy : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmpy($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011010; @@ -4676,7 +4676,7 @@ def F2_sfrecipa : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", -tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5T]> { +tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011111; @@ -4689,7 +4689,7 @@ def F2_sfsub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfsub($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4943,7 +4943,7 @@ def J2_jumpf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if (!$Pu4) jump $Ii", -tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> { +tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5005,7 +5005,7 @@ def J2_jumpfpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:t $Ii", -tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { +tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b1; @@ -5067,7 +5067,7 @@ def J2_jumprf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr $Rs32", -tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> { +tc_e0739b8c, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5115,7 +5115,7 @@ def J2_jumprfpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:t $Rs32", -tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { +tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011011; @@ -5260,7 +5260,7 @@ def J2_jumprt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr $Rs32", -tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> { +tc_e0739b8c, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5306,7 +5306,7 @@ def J2_jumprtpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:t $Rs32", -tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { +tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011010; @@ -5385,7 +5385,7 @@ def J2_jumpt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if ($Pu4) jump $Ii", -tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> { +tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5445,7 +5445,7 @@ def J2_jumptpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:t $Ii", -tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { +tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b0; @@ -13396,7 +13396,7 @@ def L4_return_map_to_raw_f : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4) dealloc_return", -tc_513bef45, TypeMAPPING>, Requires<[HasV65T]> { +tc_513bef45, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13404,7 +13404,7 @@ def L4_return_map_to_raw_fnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:nt", -tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> { +tc_395dc00f, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13412,7 +13412,7 @@ def L4_return_map_to_raw_fnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:t", -tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> { +tc_395dc00f, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13420,7 +13420,7 @@ def L4_return_map_to_raw_t : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4) dealloc_return", -tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65T]> { +tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13428,7 +13428,7 @@ def L4_return_map_to_raw_tnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:nt", -tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> { +tc_e7624c08, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13436,7 +13436,7 @@ def L4_return_map_to_raw_tnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:t", -tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> { +tc_e7624c08, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13590,7 +13590,7 @@ def L6_deallocframe_map_to_raw : HInst< (outs), (ins), "deallocframe", -tc_d1090e34, TypeMAPPING>, Requires<[HasV65T]> { +tc_d1090e34, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13598,7 +13598,7 @@ def L6_return_map_to_raw : HInst< (outs), (ins), "dealloc_return", -tc_3d04548d, TypeMAPPING>, Requires<[HasV65T]> { +tc_3d04548d, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -16978,7 +16978,7 @@ def M4_cmpyi_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17004,7 +17004,7 @@ def M4_cmpyr_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17357,7 +17357,7 @@ def M5_vdmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", -tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5T]> { +tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17369,7 +17369,7 @@ def M5_vdmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", -tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5T]> { +tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17464,7 +17464,7 @@ def M6_vabsdiffb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffb($Rtt32,$Rss32)", -tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { +tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -17474,7 +17474,7 @@ def M6_vabsdiffub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffub($Rtt32,$Rss32)", -tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { +tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -18204,7 +18204,7 @@ def S2_asr_i_p_rnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii):rnd", -tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18213,7 +18213,7 @@ def S2_asr_i_p_rnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asrrnd($Rss32,#$Ii)", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { let isPseudo = 1; } def S2_asr_i_r : HInst< @@ -25148,7 +25148,7 @@ def S5_asrhub_rnd_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):raw", -tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> { let Inst{7-5} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25161,7 +25161,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25170,7 +25170,7 @@ def S5_asrhub_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):sat", -tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> { let Inst{7-5} = 0b101; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25183,7 +25183,7 @@ def S5_popcountp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = popcount($Rss32)", -tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -25194,7 +25194,7 @@ def S5_vasrhrnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):raw", -tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5]> { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000001; @@ -25204,14 +25204,14 @@ def S5_vasrhrnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):rnd", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { let isPseudo = 1; } def S6_allocframe_to_raw : HInst< (outs), (ins u11_3Imm:$Ii), "allocframe(#$Ii)", -tc_e216a5db, TypeMAPPING>, Requires<[HasV65T]> { +tc_e216a5db, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -25219,7 +25219,7 @@ def S6_rol_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = rol($Rss32,#$Ii)", -tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> { +tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000000000; } @@ -25227,7 +25227,7 @@ def S6_rol_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += rol($Rss32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25237,7 +25237,7 @@ def S6_rol_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= rol($Rss32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25247,7 +25247,7 @@ def S6_rol_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= rol($Rss32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25257,7 +25257,7 @@ def S6_rol_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= rol($Rss32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25267,7 +25267,7 @@ def S6_rol_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= rol($Rss32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -25277,7 +25277,7 @@ def S6_rol_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = rol($Rs32,#$Ii)", -tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> { +tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -25288,7 +25288,7 @@ def S6_rol_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += rol($Rs32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25301,7 +25301,7 @@ def S6_rol_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= rol($Rs32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25314,7 +25314,7 @@ def S6_rol_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= rol($Rs32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25327,7 +25327,7 @@ def S6_rol_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= rol($Rs32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25340,7 +25340,7 @@ def S6_rol_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= rol($Rs32,#$Ii)", -tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -25353,7 +25353,7 @@ def S6_vsplatrbp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplatb($Rs32)", -tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> { +tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100010; } @@ -25361,7 +25361,7 @@ def S6_vtrunehb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunehb($Rss32,$Rtt32)", -tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { +tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -25370,7 +25370,7 @@ def S6_vtrunohb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunohb($Rss32,$Rtt32)", -tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { +tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -26350,7 +26350,7 @@ def V6_ldntnt0 : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T]> { +PSEUDO, TypeMAPPING>, Requires<[HasV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30363,7 +30363,7 @@ def V6_vasrhbrndsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30397,7 +30397,7 @@ def V6_vasrhubrndsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30419,7 +30419,7 @@ def V6_vasrhubsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30562,7 +30562,7 @@ def V6_vasrwh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30584,7 +30584,7 @@ def V6_vasrwhrndsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30606,7 +30606,7 @@ def V6_vasrwhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30640,7 +30640,7 @@ def V6_vasrwuhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", -tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { +tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -37004,7 +37004,7 @@ def Y5_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "l2fetch($Rs32,$Rtt32)", -tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5T]> { +tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5]> { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; diff --git a/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp b/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp index 253f09d..63ec9c3 100644 --- a/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp @@ -62,7 +62,7 @@ bool HexagonGatherPacketize::runOnMachineFunction(MachineFunction &Fn) { if (!EnableGatherPacketize) return false; auto &ST = Fn.getSubtarget(); - bool HasV65 = ST.hasV65TOps(); + bool HasV65 = ST.hasV65Ops(); bool UseHVX = ST.useHVXOps(); if (!(HasV65 & UseHVX)) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index bf3a7b6..4777dc3 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -432,7 +432,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } - if (NeedsArgAlign && Subtarget.hasV60TOps()) { + if (NeedsArgAlign && Subtarget.hasV60Ops()) { LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); @@ -1225,7 +1225,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST) : TargetLowering(TM), HTM(static_cast(TM)), Subtarget(ST) { - bool IsV4 = !Subtarget.hasV5TOps(); + bool IsV4 = !Subtarget.hasV5Ops(); auto &HRI = *Subtarget.getRegisterInfo(); setPrefLoopAlignment(4); @@ -1267,7 +1267,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); - if (Subtarget.hasV5TOps()) { + if (Subtarget.hasV5Ops()) { addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); } @@ -1510,11 +1510,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, // Subtarget-specific operation actions. // - if (Subtarget.hasV60TOps()) { + if (Subtarget.hasV60Ops()) { setOperationAction(ISD::ROTL, MVT::i32, Custom); setOperationAction(ISD::ROTL, MVT::i64, Custom); } - if (Subtarget.hasV5TOps()) { + if (Subtarget.hasV5Ops()) { setOperationAction(ISD::FMA, MVT::f64, Expand); setOperationAction(ISD::FADD, MVT::f64, Expand); setOperationAction(ISD::FSUB, MVT::f64, Expand); @@ -1645,7 +1645,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); } - if (Subtarget.hasV5TOps()) { + if (Subtarget.hasV5Ops()) { if (FastMath) setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf"); else @@ -2925,7 +2925,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( case 512: return {0u, &Hexagon::HvxVRRegClass}; case 1024: - if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps()) + if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps()) return {0u, &Hexagon::HvxVRRegClass}; return {0u, &Hexagon::HvxWRRegClass}; case 2048: @@ -2944,7 +2944,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { - return Subtarget.hasV5TOps(); + return Subtarget.hasV5Ops(); } /// isLegalAddressingMode - Return true if the addressing mode represented by diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td index 14bda0e..1347a65 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -19,4 +19,4 @@ class CVI_VA_Resource pattern = [], string cstr = "", InstrItinClass itin = CVI_VA> : InstHexagon, - OpcodeHexagon, Requires<[HasV60T, UseHVX]>; + OpcodeHexagon, Requires<[HasV60, UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index dad314f..6019c7c 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1600,7 +1600,7 @@ bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const { } // HVX loads are not predicable on v60, but are on v62. - if (!Subtarget.hasV62TOps()) { + if (!Subtarget.hasV62Ops()) { switch (MI.getOpcode()) { case Hexagon::V6_vL32b_ai: case Hexagon::V6_vL32b_pi: @@ -2988,7 +2988,7 @@ bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B) bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const { const uint64_t F = MI.getDesc().TSFlags; return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) && - Subtarget.hasV60TOps(); + Subtarget.hasV60Ops(); } // Returns true, if a ST insn can be promoted to a new-value store. @@ -3646,7 +3646,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const { assert(NewOp >= 0 && "Couldn't change new-value store to its old form."); } - if (Subtarget.hasV60TOps()) + if (Subtarget.hasV60Ops()) return NewOp; // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps. diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td index f27a63e..29f67cf 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -9,7 +9,7 @@ //Rdd[+]=vrmpybsu(Rss,Rtt) //Rdd[+]=vrmpybuu(Rss,Rtt) -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def : T_PP_pat ; def : T_PP_pat ; diff --git a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td index 718d3ac..c29a75e6 100644 --- a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td +++ b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td @@ -7,80 +7,80 @@ // //===----------------------------------------------------------------------===// -def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65T]>; -def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vdd0), (V6_vdd0)>, Requires<[HasV65T, UseHVX]>; -def: Pat<(int_hexagon_V6_vdd0_128B), (V6_vdd0)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>; +def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vdd0), (V6_vdd0)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vdd0_128B), (V6_vdd0)>, Requires<[HasV65, UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index b1f1c59d..e777fda 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -348,7 +348,7 @@ def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; // --(2) Type cast ------------------------------------------------------- // -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: OpR_R_pat, f64, F32>; def: OpR_R_pat, f32, F64>; @@ -374,7 +374,7 @@ let Predicates = [HasV5T] in { } // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; @@ -582,7 +582,7 @@ def: OpR_RR_pat, v2i1, V2I32>; def: OpR_RR_pat; def: OpR_RR_pat; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: OpR_RR_pat; def: OpR_RR_pat; def: OpR_RR_pat; @@ -729,7 +729,7 @@ class Cmpud: T3; class Cmpufn: T3; class Cmpudn: T3; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: OpmR_RR_pat, setueq, i1, F32>; def: OpmR_RR_pat, setuge, i1, F32>; def: OpmR_RR_pat, setugt, i1, F32>; @@ -745,7 +745,7 @@ let Predicates = [HasV5T] in { def: OpmR_RR_pat, setune, i1, F64>; } -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: OpmR_RR_pat, setone, i1, F32>; def: OpmR_RR_pat, setne, i1, F32>; @@ -784,7 +784,7 @@ def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), @@ -872,7 +872,7 @@ let AddedComplexity = 200 in { defm: SelMinMax_pats; } -let AddedComplexity = 100, Predicates = [HasV5T] in { +let AddedComplexity = 100, Predicates = [HasV5] in { defm: SelMinMax_pats; defm: SelMinMax_pats; defm: SelMinMax_pats; @@ -928,7 +928,7 @@ def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; let AddedComplexity = 10 in def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, - Requires<[HasV62T]>; + Requires<[HasV62]>; def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; @@ -989,7 +989,7 @@ def: OpR_RR_pat; def: OpR_RR_pat; def: OpR_RR_pat; -let Predicates = [HasV60T] in { +let Predicates = [HasV60] in { def: OpR_RI_pat; def: OpR_RI_pat; } @@ -997,7 +997,7 @@ let Predicates = [HasV60T] in { def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), - (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5T]>; + (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5]>; // Prefer S2_addasl_rrri over S2_asl_i_r_acc. let AddedComplexity = 120 in @@ -1039,7 +1039,7 @@ let AddedComplexity = 100 in { def: AccRRI_pat, I64, u6_0ImmPred>; def: AccRRI_pat, I64, u6_0ImmPred>; - let Predicates = [HasV60T] in { + let Predicates = [HasV60] in { def: AccRRI_pat, I32, u5_0ImmPred>; def: AccRRI_pat, I32, u5_0ImmPred>; def: AccRRI_pat, I32, u5_0ImmPred>; @@ -1182,7 +1182,7 @@ def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; @@ -1258,7 +1258,7 @@ def: OpR_RR_pat; def: OpR_RR_pat; def: OpR_RR_pat; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: OpR_RR_pat, f32, F32>; def: OpR_RR_pat, f32, F32>; def: OpR_RR_pat, f32, F32>; @@ -1497,7 +1497,7 @@ def: Pat<(add I32:$Ru, (Su I32:$Ry, I32:$Rs)), (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; -let Predicates = [HasV5T] in { +let Predicates = [HasV5] in { def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), @@ -1532,13 +1532,13 @@ def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), // Multiplies two v4i8 vectors. def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>, - Requires<[HasV5T]>; + Requires<[HasV5]>; // Multiplies two v8i8 vectors. def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>, - Requires<[HasV5T]>; + Requires<[HasV5]>; // --(10) Bit ------------------------------------------------------------ diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index 1624290..a4cfca9 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -414,7 +414,7 @@ class HvxSel_pat : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt), (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>; -let Predicates = [HasV60T,UseHVX] in { +let Predicates = [UseHVX] in { def: HvxSel_pat; def: HvxSel_pat; def: HvxSel_pat; diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index ede27c1..fd74663 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -406,42 +406,42 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { } // Vector store pseudos -let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1, +let Predicates = [HasV60,UseHVX], isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in class STrivv_template : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", [], "", rootInst.Itinerary, rootInst.Type>; def PS_vstorerw_ai: STrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; def PS_vstorerw_nt_ai: STrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; def PS_vstorerwu_ai: STrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in def PS_vstorerq_ai: Pseudo<(outs), (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; // Vector load pseudos -let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1, +let Predicates = [HasV60, UseHVX], isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in class LDrivv_template : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", [], "", rootInst.Itinerary, rootInst.Type>; def PS_vloadrw_ai: LDrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; def PS_vloadrw_nt_ai: LDrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; def PS_vloadrwu_ai: LDrivv_template, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd), (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in @@ -450,10 +450,10 @@ class VSELInst def PS_vselect: VSELInst<(outs HvxVR:$dst), (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; def PS_wselect: VSELInst<(outs HvxWR:$dst), (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>, - Requires<[HasV60T,UseHVX]>; + Requires<[HasV60,UseHVX]>; let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, isCodeGenOnly = 1 in { diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 14e2bf8..864289f 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -110,7 +110,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { UseHVX64BOps = false; UseLongCalls = false; - UseBSBScheduling = hasV60TOps() && EnableBSBSched; + UseBSBScheduling = hasV60Ops() && EnableBSBSched; ParseSubtargetFeatures(CPUString, FS); @@ -334,7 +334,7 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, return; } - if (!hasV60TOps()) + if (!hasV60Ops()) return; // Set the latency for a copy to zero since we hope that is will get removed. @@ -405,7 +405,7 @@ void HexagonSubtarget::updateLatency(MachineInstr &SrcInst, return; } - if (!hasV60TOps()) + if (!hasV60Ops()) return; auto &QII = static_cast(*getInstrInfo()); @@ -529,13 +529,13 @@ bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst, // Reassign the latency for the previous bests, which requires setting // the dependence edge in both directions. if (SrcBest != nullptr) { - if (!hasV60TOps()) + if (!hasV60Ops()) changeLatency(SrcBest, Dst, 1); else restoreLatency(SrcBest, Dst); } if (DstBest != nullptr) { - if (!hasV60TOps()) + if (!hasV60Ops()) changeLatency(Src, DstBest, 1); else restoreLatency(Src, DstBest); diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 2471cde..dc8d173 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -120,34 +120,34 @@ public: /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - bool hasV5TOps() const { + bool hasV5Ops() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V5; } - bool hasV5TOpsOnly() const { + bool hasV5OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V5; } - bool hasV55TOps() const { + bool hasV55Ops() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V55; } - bool hasV55TOpsOnly() const { + bool hasV55OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V55; } - bool hasV60TOps() const { + bool hasV60Ops() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; } - bool hasV60TOpsOnly() const { + bool hasV60OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V60; } - bool hasV62TOps() const { + bool hasV62Ops() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V62; } - bool hasV62TOpsOnly() const { + bool hasV62OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V62; } - bool hasV65TOps() const { + bool hasV65Ops() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V65; } - bool hasV65TOpsOnly() const { + bool hasV65OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V65; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index ae97471..56ab69d 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1098,7 +1098,7 @@ bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) { static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII) { const MachineFunction *MF = MI.getParent()->getParent(); - if (MF->getSubtarget().hasV60TOpsOnly() && + if (MF->getSubtarget().hasV60OpsOnly() && HII.isHVXMemWithAIndirect(MI, MJ)) return true; @@ -1520,7 +1520,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { bool IsVecJ = HII->isHVXVec(J); bool IsVecI = HII->isHVXVec(I); - if (Slot1Store && MF.getSubtarget().hasV65TOps() && + if (Slot1Store && MF.getSubtarget().hasV65Ops() && ((LoadJ && StoreI && !NVStoreI) || (StoreJ && LoadI && !NVStoreJ)) && (J.getOpcode() != Hexagon::S2_allocframe && -- 2.7.4