From d891d738d9b8d87897d9309da98692133b7ba46a Mon Sep 17 00:00:00 2001 From: Rahul Joshi Date: Wed, 24 Jun 2020 11:49:30 -0700 Subject: [PATCH] [MLIR][NFC] Adopt variadic isa<> Differential Revision: https://reviews.llvm.org/D82489 --- mlir/lib/Analysis/AffineAnalysis.cpp | 3 +-- mlir/lib/Analysis/LoopAnalysis.cpp | 3 +-- mlir/lib/Analysis/NestedMatcher.cpp | 2 +- mlir/lib/Analysis/SliceAnalysis.cpp | 3 +-- mlir/lib/Analysis/Utils.cpp | 2 +- mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 7 +++---- mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp | 6 ++---- .../Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp | 5 +---- mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp | 2 +- mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp | 2 +- mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp | 7 +++---- mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp | 2 +- mlir/lib/Dialect/SCF/SCF.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp | 8 +++----- mlir/lib/Interfaces/SideEffectInterfaces.cpp | 3 +-- mlir/lib/Pass/IRPrinting.cpp | 2 +- mlir/lib/TableGen/Dialect.cpp | 3 +-- mlir/lib/TableGen/Operator.cpp | 2 +- mlir/lib/TableGen/Pattern.cpp | 2 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 2 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 2 +- mlir/lib/Transforms/LoopFusion.cpp | 6 ++---- mlir/lib/Transforms/MemRefDataFlowOpt.cpp | 2 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 2 +- mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 4 ++-- mlir/lib/Transforms/Utils/Utils.cpp | 6 ++---- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 2 +- 29 files changed, 39 insertions(+), 57 deletions(-) diff --git a/mlir/lib/Analysis/AffineAnalysis.cpp b/mlir/lib/Analysis/AffineAnalysis.cpp index ca662c71..044c85d 100644 --- a/mlir/lib/Analysis/AffineAnalysis.cpp +++ b/mlir/lib/Analysis/AffineAnalysis.cpp @@ -859,8 +859,7 @@ void mlir::getDependenceComponents( // Collect all load and store ops in loop nest rooted at 'forOp'. SmallVector loadAndStoreOpInsts; forOp.getOperation()->walk([&](Operation *opInst) { - if (isa(opInst) || - isa(opInst)) + if (isa(opInst)) loadAndStoreOpInsts.push_back(opInst); }); diff --git a/mlir/lib/Analysis/LoopAnalysis.cpp b/mlir/lib/Analysis/LoopAnalysis.cpp index 0c8ff31..8975a07 100644 --- a/mlir/lib/Analysis/LoopAnalysis.cpp +++ b/mlir/lib/Analysis/LoopAnalysis.cpp @@ -291,8 +291,7 @@ isVectorizableLoopBodyWithOpCond(AffineForOp loop, // No vectorization across unknown regions. auto regions = matcher::Op([](Operation &op) -> bool { - return op.getNumRegions() != 0 && - !(isa(op) || isa(op)); + return op.getNumRegions() != 0 && !isa(op); }); SmallVector regionsMatched; regions.match(forOp, ®ionsMatched); diff --git a/mlir/lib/Analysis/NestedMatcher.cpp b/mlir/lib/Analysis/NestedMatcher.cpp index 807e5df..e745ac7 100644 --- a/mlir/lib/Analysis/NestedMatcher.cpp +++ b/mlir/lib/Analysis/NestedMatcher.cpp @@ -145,7 +145,7 @@ NestedPattern For(FilterFunctionType filter, ArrayRef nested) { } bool isLoadOrStore(Operation &op) { - return isa(op) || isa(op); + return isa(op); } } // end namespace matcher diff --git a/mlir/lib/Analysis/SliceAnalysis.cpp b/mlir/lib/Analysis/SliceAnalysis.cpp index e0c828f..a09fcf4 100644 --- a/mlir/lib/Analysis/SliceAnalysis.cpp +++ b/mlir/lib/Analysis/SliceAnalysis.cpp @@ -85,8 +85,7 @@ static void getBackwardSliceImpl(Operation *op, if (!op) return; - assert((op->getNumRegions() == 0 || isa(op) || - isa(op)) && + assert((op->getNumRegions() == 0 || isa(op)) && "unexpected generic op with regions"); // Evaluate whether we should keep this def. diff --git a/mlir/lib/Analysis/Utils.cpp b/mlir/lib/Analysis/Utils.cpp index 40a45ce..8a29fdb 100644 --- a/mlir/lib/Analysis/Utils.cpp +++ b/mlir/lib/Analysis/Utils.cpp @@ -196,7 +196,7 @@ LogicalResult MemRefRegion::unionBoundingBox(const MemRefRegion &other) { LogicalResult MemRefRegion::compute(Operation *op, unsigned loopDepth, ComputationSliceState *sliceState, bool addMemRefDimBounds) { - assert((isa(op) || isa(op)) && + assert((isa(op)) && "affine read/write op expected"); MemRefAccess access(op); diff --git a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp index ed3623a..8893ef5 100644 --- a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp +++ b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp @@ -141,9 +141,8 @@ bool mlir::isValidDim(Value value) { // This value has to be a block argument for an op that has the // `AffineScope` trait or for an affine.for or affine.parallel. auto *parentOp = value.cast().getOwner()->getParentOp(); - return parentOp && - (parentOp->hasTrait() || - isa(parentOp) || isa(parentOp)); + return parentOp && (parentOp->hasTrait() || + isa(parentOp)); } // Value can be used as a dimension id iff it meets one of the following @@ -165,7 +164,7 @@ bool mlir::isValidDim(Value value, Region *region) { // This value has to be a block argument for an affine.for or an // affine.parallel. auto *parentOp = value.cast().getOwner()->getParentOp(); - return isa(parentOp) || isa(parentOp); + return isa(parentOp); } // Affine apply operation is ok if all of its operands are ok. diff --git a/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp b/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp index 78128ff..89cbca0 100644 --- a/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp @@ -120,8 +120,7 @@ AffineDataCopyGeneration::runOnBlock(Block *block, // Get to the first load, store, or for op (that is not a copy nest itself). auto curBegin = std::find_if(block->begin(), block->end(), [&](Operation &op) { - return (isa(op) || isa(op) || - isa(op)) && + return isa(op) && copyNests.count(&op) == 0; }); @@ -171,8 +170,7 @@ AffineDataCopyGeneration::runOnBlock(Block *block, } // Get to the next load or store op after 'forOp'. curBegin = std::find_if(std::next(it), block->end(), [&](Operation &op) { - return (isa(op) || isa(op) || - isa(op)) && + return isa(op) && copyNests.count(&op) == 0; }); it = curBegin; diff --git a/mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp b/mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp index 72e99cc..e060aac 100644 --- a/mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp @@ -63,10 +63,7 @@ areAllOpsInTheBlockListInvariant(Region &blockList, Value indVar, static bool isMemRefDereferencingOp(Operation &op) { // TODO(asabne): Support DMA Ops. - if (isa(op) || isa(op)) { - return true; - } - return false; + return isa(op); } // Returns true if the individual op is loop invariant. diff --git a/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp b/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp index fada39a..0cd59b5 100644 --- a/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp @@ -93,7 +93,7 @@ void SimplifyAffineStructures::runOnFunction() { // The simplification of the attribute will likely simplify the op. Try to // fold / apply canonicalization patterns when we have affine dialect ops. - if (isa(op) || isa(op) || isa(op)) + if (isa(op)) applyOpPatternsAndFold(op, patterns); }); diff --git a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp index f5b98f9..c47a656 100644 --- a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp @@ -561,7 +561,7 @@ makePatterns(const DenseSet ¶llelLoops, int vectorRank, static NestedPattern &vectorTransferPattern() { static auto pattern = matcher::Op([](Operation &op) { - return isa(op) || isa(op); + return isa(op); }); return pattern; } diff --git a/mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp b/mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp index 1d72f9e..1ec0f0c 100644 --- a/mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp +++ b/mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp @@ -54,7 +54,7 @@ static void injectGpuIndexOperations(Location loc, Region &launchFuncOpBody, } static bool isSinkingBeneficiary(Operation *op) { - return isa(op) || isa(op); + return isa(op); } LogicalResult mlir::sinkOperationsIntoLaunchOp(gpu::LaunchOp launchOp) { diff --git a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp index eeabdeb..485f513 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp @@ -38,7 +38,7 @@ void mlir::linalg::hoistViewAllocOps(FuncOp func) { while (changed) { changed = false; func.walk([&changed](Operation *op) { - if (!isa(op) && !isa(op) && !isa(op)) + if (!isa(op)) return; LLVM_DEBUG(DBGS() << "Candidate for hoisting: " << *op << "\n"); @@ -64,15 +64,14 @@ void mlir::linalg::hoistViewAllocOps(FuncOp func) { v = op->getResult(0); } if (v && !llvm::all_of(v.getUses(), [&](OpOperand &operand) { - return isa(operand.getOwner()) || - isa(operand.getOwner()); + return isa(operand.getOwner()); })) { LLVM_DEBUG(DBGS() << "Found non view-like or dealloc use: bail\n"); return; } // Move AllocOp before the loop. - if (isa(op) || isa(op)) + if (isa(op)) loop.moveOutOfLoop({op}); else // Move DeallocOp outside of the loop. op->moveAfter(loop); diff --git a/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp b/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp index 71e4969..b191cbe 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp @@ -37,7 +37,7 @@ LogicalResult mlir::linalg::interchangeGenericLinalgOpPrecondition( if (interchangeVector.empty()) return failure(); // Transformation applies to generic ops only. - if (!isa(op) && !isa(op)) + if (!isa(op)) return failure(); LinalgOp linOp = cast(op); // Transformation applies to buffers only. diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index 7639613..07de495 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -76,7 +76,7 @@ LogicalResult mlir::linalg::vectorizeLinalgOpPrecondition(Operation *op) { for (Type outputTensorType : linalgOp.getOutputTensorTypes()) if (!outputTensorType.cast().hasStaticShape()) return failure(); - if (isa(op) || isa(op)) + if (isa(op)) return success(); auto genericOp = dyn_cast(op); diff --git a/mlir/lib/Dialect/SCF/SCF.cpp b/mlir/lib/Dialect/SCF/SCF.cpp index 559a5f1..4484fdf 100644 --- a/mlir/lib/Dialect/SCF/SCF.cpp +++ b/mlir/lib/Dialect/SCF/SCF.cpp @@ -831,7 +831,7 @@ static LogicalResult verify(YieldOp op) { auto results = parentOp->getResults(); auto operands = op.getOperands(); - if (isa(parentOp) || isa(parentOp)) { + if (isa(parentOp)) { if (parentOp->getNumResults() != op.getNumOperands()) return op.emitOpError() << "parent of yield must have same number of " "results as the yield operands"; diff --git a/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp index 43e70a1..894de3d 100644 --- a/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp +++ b/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp @@ -45,8 +45,7 @@ using namespace mlir::spirv; static inline bool containsReturn(Region ®ion) { return llvm::any_of(region, [](Block &block) { Operation *terminator = block.getTerminator(); - return isa(terminator) || - isa(terminator); + return isa(terminator); }); } @@ -62,8 +61,7 @@ struct SPIRVInlinerInterface : public DialectInlinerInterface { // Return true here when inlining into spv.func, spv.selection, and // spv.loop operations. auto *op = dest->getParentOp(); - return isa(op) || isa(op) || - isa(op); + return isa(op); } /// Returns true if the given operation 'op', that is registered to this @@ -72,7 +70,7 @@ struct SPIRVInlinerInterface : public DialectInlinerInterface { bool isLegalToInline(Operation *op, Region *dest, BlockAndValueMapping &) const final { // TODO(antiagainst): Enable inlining structured control flows with return. - if ((isa(op) || isa(op)) && + if ((isa(op)) && containsReturn(op->getRegion(0))) return false; // TODO(antiagainst): we need to filter OpKill here to avoid inlining it to diff --git a/mlir/lib/Interfaces/SideEffectInterfaces.cpp b/mlir/lib/Interfaces/SideEffectInterfaces.cpp index 1d40f1d..89b2b34 100644 --- a/mlir/lib/Interfaces/SideEffectInterfaces.cpp +++ b/mlir/lib/Interfaces/SideEffectInterfaces.cpp @@ -22,8 +22,7 @@ using namespace mlir; //===----------------------------------------------------------------------===// bool MemoryEffects::Effect::classof(const SideEffects::Effect *effect) { - return isa(effect) || isa(effect) || isa(effect) || - isa(effect); + return isa(effect); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Pass/IRPrinting.cpp b/mlir/lib/Pass/IRPrinting.cpp index 1e97605..c27e47f 100644 --- a/mlir/lib/Pass/IRPrinting.cpp +++ b/mlir/lib/Pass/IRPrinting.cpp @@ -97,7 +97,7 @@ private: /// Returns true if the given pass is hidden from IR printing. static bool isHiddenPass(Pass *pass) { - return isa(pass) || isa(pass); + return isa(pass); } static void printIR(Operation *op, bool printModuleScope, raw_ostream &out, diff --git a/mlir/lib/TableGen/Dialect.cpp b/mlir/lib/TableGen/Dialect.cpp index db68ed4..25be9fa 100644 --- a/mlir/lib/TableGen/Dialect.cpp +++ b/mlir/lib/TableGen/Dialect.cpp @@ -34,8 +34,7 @@ std::string tblgen::Dialect::getCppClassName() const { static StringRef getAsStringOrEmpty(const llvm::Record &record, StringRef fieldName) { if (auto valueInit = record.getValueInit(fieldName)) { - if (llvm::isa(valueInit) || - llvm::isa(valueInit)) + if (llvm::isa(valueInit)) return record.getValueAsString(fieldName); } return ""; diff --git a/mlir/lib/TableGen/Operator.cpp b/mlir/lib/TableGen/Operator.cpp index 534219b..8350cd1 100644 --- a/mlir/lib/TableGen/Operator.cpp +++ b/mlir/lib/TableGen/Operator.cpp @@ -558,7 +558,7 @@ StringRef tblgen::Operator::getSummary() const { bool tblgen::Operator::hasAssemblyFormat() const { auto *valueInit = def.getValueInit("assemblyFormat"); - return isa(valueInit) || isa(valueInit); + return isa(valueInit); } StringRef tblgen::Operator::getAssemblyFormat() const { diff --git a/mlir/lib/TableGen/Pattern.cpp b/mlir/lib/TableGen/Pattern.cpp index b04c8e2..c2b86b8 100644 --- a/mlir/lib/TableGen/Pattern.cpp +++ b/mlir/lib/TableGen/Pattern.cpp @@ -57,7 +57,7 @@ bool tblgen::DagLeaf::isEnumAttrCase() const { } bool tblgen::DagLeaf::isStringAttr() const { - return isa(def) || isa(def); + return isa(def); } tblgen::Constraint tblgen::DagLeaf::getAsConstraint() const { diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp index 60514ca..94bd8bd 100644 --- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp +++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp @@ -106,7 +106,7 @@ private: /// Globals are inserted before the first function, if any. Block::iterator getGlobalInsertPt() { auto i = module.getBody()->begin(); - while (!isa(i) && !isa(i)) + while (!isa(i)) ++i; return i; } diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index 8e022f5..9d2aeb8 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -129,7 +129,7 @@ llvm::Constant *ModuleTranslation::getLLVMConstant(llvm::Type *llvmType, // another sequence type. The recursion terminates because each step removes // one outer sequential type. bool elementTypeSequential = - isa(elementType) || isa(elementType); + isa(elementType); llvm::Constant *child = getLLVMConstant( elementType, elementTypeSequential ? splatAttr : splatAttr.getSplatValue(), loc); diff --git a/mlir/lib/Transforms/LoopFusion.cpp b/mlir/lib/Transforms/LoopFusion.cpp index 4ca27b4..6a7a88e 100644 --- a/mlir/lib/Transforms/LoopFusion.cpp +++ b/mlir/lib/Transforms/LoopFusion.cpp @@ -70,10 +70,8 @@ mlir::createLoopFusionPass(unsigned fastMemorySpace, // TODO(b/117228571) Replace when this is modeled through side-effects/op traits static bool isMemRefDereferencingOp(Operation &op) { - if (isa(op) || isa(op) || - isa(op) || isa(op)) - return true; - return false; + return isa(op); } namespace { diff --git a/mlir/lib/Transforms/MemRefDataFlowOpt.cpp b/mlir/lib/Transforms/MemRefDataFlowOpt.cpp index 2b288d3..75ac0a5 100644 --- a/mlir/lib/Transforms/MemRefDataFlowOpt.cpp +++ b/mlir/lib/Transforms/MemRefDataFlowOpt.cpp @@ -207,7 +207,7 @@ void MemRefDataFlowOpt::runOnFunction() { // could still erase it if the call had no side-effects. continue; if (llvm::any_of(memref.getUsers(), [&](Operation *ownerOp) { - return (!isa(ownerOp) && !isa(ownerOp)); + return !isa(ownerOp); })) continue; diff --git a/mlir/lib/Transforms/PipelineDataTransfer.cpp b/mlir/lib/Transforms/PipelineDataTransfer.cpp index d4a5ba9..cb27036 100644 --- a/mlir/lib/Transforms/PipelineDataTransfer.cpp +++ b/mlir/lib/Transforms/PipelineDataTransfer.cpp @@ -48,7 +48,7 @@ std::unique_ptr> mlir::createPipelineDataTransferPass() { // Temporary utility: will be replaced when DmaStart/DmaFinish abstract op's are // added. TODO(b/117228571) static unsigned getTagMemRefPos(Operation &dmaOp) { - assert(isa(dmaOp) || isa(dmaOp)); + assert((isa(dmaOp))); if (auto dmaStartOp = dyn_cast(dmaOp)) { return dmaStartOp.getTagMemRefOperandIndex(); } diff --git a/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp b/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp index c40e3e2..2a735a5 100644 --- a/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp +++ b/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp @@ -105,7 +105,7 @@ static Operation *getLastDependentOpInRange(Operation *opA, Operation *opB) { it != Block::reverse_iterator(opA); ++it) { Operation *opX = &(*it); opX->walk([&](Operation *op) { - if (isa(op) || isa(op)) { + if (isa(op)) { if (isDependentLoadOrStoreOp(op, values)) { lastDepOp = opX; return WalkResult::interrupt(); @@ -179,7 +179,7 @@ gatherLoadsAndStores(AffineForOp forOp, SmallVectorImpl &loadAndStoreOps) { bool hasIfOp = false; forOp.walk([&](Operation *op) { - if (isa(op) || isa(op)) + if (isa(op)) loadAndStoreOps.push_back(op); else if (isa(op)) hasIfOp = true; diff --git a/mlir/lib/Transforms/Utils/Utils.cpp b/mlir/lib/Transforms/Utils/Utils.cpp index 358d554..86bf4da 100644 --- a/mlir/lib/Transforms/Utils/Utils.cpp +++ b/mlir/lib/Transforms/Utils/Utils.cpp @@ -30,10 +30,8 @@ using namespace mlir; // Temporary utility: will be replaced when this is modeled through // side-effects/op traits. TODO(b/117228571) static bool isMemRefDereferencingOp(Operation &op) { - if (isa(op) || isa(op) || - isa(op) || isa(op)) - return true; - return false; + return isa(op); } /// Return the AffineMapAttr associated with memory 'op' on 'memref'. diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp index 6aa7b01..e477c56 100644 --- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp +++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp @@ -131,7 +131,7 @@ static std::string replaceAllSubstrs(std::string str, const std::string &match, static inline bool hasStringAttribute(const Record &record, StringRef fieldName) { auto valueInit = record.getValueInit(fieldName); - return isa(valueInit) || isa(valueInit); + return isa(valueInit); } static std::string getArgumentName(const Operator &op, int index) { -- 2.7.4