From d87d0c930a1591617e4c7c78296b4ba029150188 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:45:58 +0100 Subject: [PATCH] [MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency. Signed-off-by: Ralf Baechle --- arch/mips/kernel/smtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index fe22387..137183b 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv) " addu %1, %0, 1 \n" " sc %1, %2 \n" " beqz %1, 1b \n" - " sync \n" + __WEAK_LLSC_MB : "=&r" (result), "=&r" (temp), "=m" (*pv) : "m" (*pv) : "memory"); -- 2.7.4