From d85eb528c4405cf8d1fd109fd06ab8c418e47744 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Wed, 3 Aug 1994 16:32:47 +0000 Subject: [PATCH] Rearranged structure so machine-dependent portion is laid out like `struct mips_thread_state; struct mips_exc_state; struct mips_float_state;'. --- sysdeps/mach/hurd/mips/sigcontext.h | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/sysdeps/mach/hurd/mips/sigcontext.h b/sysdeps/mach/hurd/mips/sigcontext.h index 2cb9459..ca86a2f 100644 --- a/sysdeps/mach/hurd/mips/sigcontext.h +++ b/sysdeps/mach/hurd/mips/sigcontext.h @@ -31,11 +31,31 @@ struct sigcontext /* Port this thread is doing an interruptible RPC on. */ unsigned int sc_intr_port; - /* These four elements are laid out just like a `struct mips_thread_state'; + /* The rest of this structure is written to be laid out identically + to: + { + struct mips_thread_state ts; + struct mips_exc_state es; + struct mips_float_state fs; + } trampoline.c knows this, so it must be changed if this changes. */ int sc_gpr[31]; /* "General" registers; [0] is r1. */ - int sc_pc; /* Instruction pointer. */ int sc_mdlo, sc_mdhi; /* High and low multiplication results. */ + int sc_pc; /* Instruction pointer. */ - int sc_ps; /* Processor status. */ + /* struct mips_exc_state */ + unsigned int sc_cause; /* Machine-level trap code. */ +#define SC_CAUSE_SST 0x00000044 + unsigned int sc_badvaddr; + unsigned int sc_coproc_used; /* Which coprocessors the thread has used. */ +#define SC_COPROC_USE_COP0 1 /* (by definition) */ +#define SC_COPROC_USE_COP1 2 /* FPA */ +#define SC_COPROC_USE_FPU SC_COPROC_USE_COP1 +#define SC_COPROC_USE_COP2 4 +#define SC_COPROC_USE_COP3 8 + + /* struct mips_float_state */ + int sc_fpr[32]; /* FP registers. */ + int sc_fpcsr; /* FPU status register. */ + int sc_fpeir; /* FP exception instruction register. */ }; -- 2.7.4