From d7762a3b369ec2be8ccb5f585aa6a96026caaa33 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 10 Mar 2021 09:13:43 +0000 Subject: [PATCH] [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11 Differential Revision: https://reviews.llvm.org/D128189 --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 4 ++-- llvm/test/CodeGen/AMDGPU/s_code_end.ll | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index bcb10b8..0781334 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -301,7 +301,7 @@ bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { uint32_t Encoded_pad = Encoded_s_code_end; // Instruction cache line size in bytes. - const unsigned Log2CacheLineSize = 6; + const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; const unsigned CacheLineSize = 1u << Log2CacheLineSize; // Extra padding amount in bytes to support prefetch mode 3. @@ -824,7 +824,7 @@ bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { uint32_t Encoded_pad = Encoded_s_code_end; // Instruction cache line size in bytes. - const unsigned Log2CacheLineSize = 6; + const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; const unsigned CacheLineSize = 1u << Log2CacheLineSize; // Extra padding amount in bytes to support prefetch mode 3. diff --git a/llvm/test/CodeGen/AMDGPU/s_code_end.ll b/llvm/test/CodeGen/AMDGPU/s_code_end.ll index 51197f3..ad7d8a1 100644 --- a/llvm/test/CodeGen/AMDGPU/s_code_end.ll +++ b/llvm/test/CodeGen/AMDGPU/s_code_end.ll @@ -41,10 +41,10 @@ define amdgpu_kernel void @a_kernel2() #0 { ; GCN-ASM-NEXT: [[END_LABEL3:\.Lfunc_end.*]]: ; GCN-ASM-NEXT: .size a_function, [[END_LABEL3]]-a_function ; GFX10END-ASM: .p2alignl 6, 3214868480 -; GFX11END-ASM: .p2alignl 6, 3214868480 +; GFX11END-ASM: .p2alignl 7, 3214868480 ; GFX90AEND-ASM: .p2alignl 6, 3212836864 ; GFX10END-ASM-NEXT: .fill 48, 4, 3214868480 -; GFX11END-ASM-NEXT: .fill 48, 4, 3214868480 +; GFX11END-ASM-NEXT: .fill 96, 4, 3214868480 ; GFX90AEND-ASM-NEXT: .fill 256, 4, 3212836864 ; GFX10NOEND-NOT: .fill ; GFX11NOEND-NOT: .fill -- 2.7.4